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Fix some RISC-V ABI issues and add ILP32/LP64 (soft float) to module tests #21610

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Oct 17, 2024
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2 changes: 1 addition & 1 deletion lib/compiler_rt/common.zig
Original file line number Diff line number Diff line change
Expand Up @@ -103,7 +103,7 @@ pub fn F16T(comptime OtherType: type) type {
else
u16,
.aarch64, .aarch64_be => f16,
.riscv64 => if (builtin.zig_backend == .stage1) u16 else f16,
.riscv32, .riscv64 => f16,
.x86, .x86_64 => if (builtin.target.isDarwin()) switch (OtherType) {
// Starting with LLVM 16, Darwin uses different abi for f16
// depending on the type of the other return/argument..???
Expand Down
32 changes: 6 additions & 26 deletions src/codegen/llvm.zig
Original file line number Diff line number Diff line change
Expand Up @@ -1687,12 +1687,6 @@ pub const Object = struct {
else
try wip.load(.normal, param_llvm_ty, arg_ptr, param_alignment, ""));
},
.as_u16 => {
assert(!it.byval_attr);
const param = wip.arg(llvm_arg_i);
llvm_arg_i += 1;
args.appendAssumeCapacity(try wip.cast(.bitcast, param, .half, ""));
},
.float_array => {
const param_ty = Type.fromInterned(fn_info.param_types.get(ip)[it.zig_index - 1]);
const param_llvm_ty = try o.lowerType(param_ty);
Expand Down Expand Up @@ -3095,7 +3089,6 @@ pub const Object = struct {
.no_bits,
.abi_sized_int,
.multiple_llvm_types,
.as_u16,
.float_array,
.i32_array,
.i64_array,
Expand Down Expand Up @@ -3770,9 +3763,6 @@ pub const Object = struct {
.multiple_llvm_types => {
try llvm_params.appendSlice(o.gpa, it.types_buffer[0..it.types_len]);
},
.as_u16 => {
try llvm_params.append(o.gpa, .i16);
},
.float_array => |count| {
const param_ty = Type.fromInterned(fn_info.param_types.get(ip)[it.zig_index - 1]);
const float_ty = try o.lowerType(aarch64_c_abi.getFloatArrayType(param_ty, zcu).?);
Expand Down Expand Up @@ -5587,12 +5577,6 @@ pub const FuncGen = struct {
llvm_args.appendAssumeCapacity(loaded);
}
},
.as_u16 => {
const arg = args[it.zig_index - 1];
const llvm_arg = try self.resolveInst(arg);
const casted = try self.wip.cast(.bitcast, llvm_arg, .i16, "");
try llvm_args.append(casted);
},
.float_array => |count| {
const arg = args[it.zig_index - 1];
const arg_ty = self.typeOf(arg);
Expand Down Expand Up @@ -5654,7 +5638,6 @@ pub const FuncGen = struct {
.no_bits,
.abi_sized_int,
.multiple_llvm_types,
.as_u16,
.float_array,
.i32_array,
.i64_array,
Expand Down Expand Up @@ -11968,7 +11951,6 @@ const ParamTypeIterator = struct {
abi_sized_int,
multiple_llvm_types,
slice,
as_u16,
float_array: u8,
i32_array: u8,
i64_array: u8,
Expand Down Expand Up @@ -12090,8 +12072,6 @@ const ParamTypeIterator = struct {
.riscv32, .riscv64 => {
it.zig_index += 1;
it.llvm_index += 1;
if (ty.toIntern() == .f16_type and
!std.Target.riscv.featureSetHas(target.cpu.features, .d)) return .as_u16;
switch (riscv_c_abi.classifyType(ty, zcu)) {
.memory => return .byref_mut,
.byval => return .byval,
Expand Down Expand Up @@ -12439,7 +12419,8 @@ fn isScalar(zcu: *Zcu, ty: Type) bool {
}

/// This function returns true if we expect LLVM to lower x86_fp80 correctly
/// and false if we expect LLVM to crash if it counters an x86_fp80 type.
/// and false if we expect LLVM to crash if it encounters an x86_fp80 type,
/// or if it produces miscompilations.
fn backendSupportsF80(target: std.Target) bool {
return switch (target.cpu.arch) {
.x86_64, .x86 => !std.Target.x86.featureSetHas(target.cpu.features, .soft_float),
Expand All @@ -12448,8 +12429,8 @@ fn backendSupportsF80(target: std.Target) bool {
}

/// This function returns true if we expect LLVM to lower f16 correctly
/// and false if we expect LLVM to crash if it counters an f16 type or
/// if it produces miscompilations.
/// and false if we expect LLVM to crash if it encounters an f16 type,
/// or if it produces miscompilations.
fn backendSupportsF16(target: std.Target) bool {
return switch (target.cpu.arch) {
.hexagon,
Expand All @@ -12463,7 +12444,6 @@ fn backendSupportsF16(target: std.Target) bool {
.mipsel,
.mips64,
.mips64el,
.riscv32,
.s390x,
=> false,
.arm,
Expand All @@ -12479,7 +12459,7 @@ fn backendSupportsF16(target: std.Target) bool {
}

/// This function returns true if we expect LLVM to lower f128 correctly,
/// and false if we expect LLVm to crash if it encounters and f128 type
/// and false if we expect LLVM to crash if it encounters an f128 type,
/// or if it produces miscompilations.
fn backendSupportsF128(target: std.Target) bool {
return switch (target.cpu.arch) {
Expand All @@ -12506,7 +12486,7 @@ fn backendSupportsF128(target: std.Target) bool {
}

/// LLVM does not support all relevant intrinsics for all targets, so we
/// may need to manually generate a libc call
/// may need to manually generate a compiler-rt call.
fn intrinsicsAllowed(scalar_ty: Type, target: std.Target) bool {
return switch (scalar_ty.toIntern()) {
.f16_type => backendSupportsF16(target),
Expand Down
19 changes: 8 additions & 11 deletions src/target.zig
Original file line number Diff line number Diff line change
Expand Up @@ -427,30 +427,27 @@ pub fn llvmMachineAbi(target: std.Target) ?[:0]const u8 {
// Once our self-hosted linker can handle both ABIs, this hack should go away.
if (target.cpu.arch == .powerpc64) return "elfv2";

const have_float = switch (target.abi) {
.gnueabihf, .musleabihf, .eabihf => true,
else => false,
};

switch (target.cpu.arch) {
.riscv64 => {
const featureSetHas = std.Target.riscv.featureSetHas;
if (featureSetHas(target.cpu.features, .d)) {
if (featureSetHas(target.cpu.features, .e)) {
return "lp64e";
} else if (featureSetHas(target.cpu.features, .d)) {
return "lp64d";
} else if (have_float) {
} else if (featureSetHas(target.cpu.features, .f)) {
return "lp64f";
} else {
return "lp64";
}
},
.riscv32 => {
const featureSetHas = std.Target.riscv.featureSetHas;
if (featureSetHas(target.cpu.features, .d)) {
if (featureSetHas(target.cpu.features, .e)) {
return "ilp32e";
} else if (featureSetHas(target.cpu.features, .d)) {
return "ilp32d";
} else if (have_float) {
} else if (featureSetHas(target.cpu.features, .f)) {
return "ilp32f";
} else if (featureSetHas(target.cpu.features, .e)) {
return "ilp32e";
} else {
return "ilp32";
}
Expand Down
30 changes: 29 additions & 1 deletion test/tests.zig
Original file line number Diff line number Diff line change
Expand Up @@ -579,6 +579,20 @@ const test_targets = blk: {
.link_libc = true,
},

.{
.target = std.Target.Query.parse(.{
.arch_os_abi = "riscv32-linux-none",
.cpu_features = "baseline-d-f",
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(The plan is for this to become a proper ABI in std.Target with #20690.)

}) catch unreachable,
},
.{
.target = std.Target.Query.parse(.{
.arch_os_abi = "riscv32-linux-musl",
.cpu_features = "baseline-d-f",
}) catch unreachable,
.link_libc = true,
},

.{
.target = .{
.cpu_arch = .riscv32,
Expand All @@ -603,6 +617,20 @@ const test_targets = blk: {
.link_libc = true,
},

.{
.target = std.Target.Query.parse(.{
.arch_os_abi = "riscv64-linux-none",
.cpu_features = "baseline-d-f",
}) catch unreachable,
},
.{
.target = std.Target.Query.parse(.{
.arch_os_abi = "riscv64-linux-musl",
.cpu_features = "baseline-d-f",
}) catch unreachable,
.link_libc = true,
},

.{
.target = .{
.cpu_arch = .riscv64,
Expand Down Expand Up @@ -631,7 +659,7 @@ const test_targets = blk: {
.target = std.Target.Query.parse(.{
.arch_os_abi = "riscv64-linux-musl",
.cpu_features = "baseline+v+zbb",
}) catch @panic("OOM"),
}) catch unreachable,
.use_llvm = false,
.use_lld = false,
},
Expand Down
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