Cookbook
欢迎来到sulp的Cookbook
- 如何初始化项目
- 如何初始化workspace
- 怎样转换verilog到与宏无关的文件状态
- 如何收集与生成SoC的仿真memory及工艺相关的db文件
- 如何快速生成SoC的系统组件
- 如何快速搭建SoC的验证环境
- 如何快速评估SoC中的模块PPA
- 如何搭建SoC的FPGA环境
- 如何搭建SoC的静态分析环境
- 如何将flow加入到持续集成flow中
- init
- git_file
- git_helper
- vpp_file
- vpp_run
- vpp_module
- mem_file
- mem_verif
- mem_report
- mem_regression
- design_syscon
- design_clkgen
- design_rstgen
- design_dmaChannel
- design_padShare
- design_interrupt
- design_dummy
- design_instance
- verif_file
- verif_case
- verif_scSuit
- verif_uvm
- verif_sim
- verif_report
- verif_regression
- verif_wave
- asic_file
- asic_syn
- asic_report
- asic_regression
- asic_view --> start_gui
- fpga_file
- fpga_syn
- fpga_imp
- fpga_report
- fpga_regression
- fpga_view --> start_gui
- signoff_file
- signoff_spyglass
- signoff_pt
- signoff_fm
- signoff_report
- signoff_regression
- ci_file
- ci_run
- ci_report