V2.5

Bug fixes in this version.

Bug fixes #8, #9, and #10.

Thanks to nepx for noticing and reporting the decoding errors.

This release Features.

Backwards compatible to 32 bit, and 16 bit.

Supports instructions sets: MMX, SSE, SSE2, SSE3, SSSE3, SSE4, SSE4a, SSE4.1, SSE4.2, SMX, VMX, AMD-V, Intel VT-x, AES, ADX, HLE, MPX, ABM, BMI1, BMI2, TBM, FMA, SHA, AVX2, AVX512F, AVX512CD, AVX512ER, AVX512PF, AVX512BW, AVX512DQ, AVX512VL, AVX512IFMA, AVX512VBMI.

Compatibility modes for older incompatible processors: Knights Corner, Intel Larrabee, Cyrix, Geode, Centaur, X86/486.

V2.4

Bug fixes in this version.

Fixes 16 bit instructions 0F 84, and 0F 85.

Fixes 16 bit instructions 8C, 8E.

Fixes 64 bit relative addresses.

This release Features.

Backwards compatible to 32 bit, and 16 bit.

Supports instructions sets: MMX, SSE, SSE2, SSE3, SSSE3, SSE4, SSE4a, SSE4.1, SSE4.2, SMX, VMX, AMD-V, Intel VT-x, AES, ADX, HLE, MPX, ABM, BMI1, BMI2, TBM, FMA, SHA, AVX2, AVX512F, AVX512CD, AVX512ER, AVX512PF, AVX512BW, AVX512DQ, AVX512VL, AVX512IFMA, AVX512VBMI.

Compatibility modes for older incompatible processors: Knights Corner, Intel Larrabee, Cyrix, Geode, Centaur, X86/486.

V2.3

Bug fixes in this version.

Fixed right shift 32 problem.

Backwards compatible to 32 bit, and 16 bit.

Supports instructions sets: MMX, SSE, SSE2, SSE3, SSSE3, SSE4, SSE4a, SSE4.1, SSE4.2, SMX, VMX, AMD-V, Intel VT-x, AES, ADX, HLE, MPX, ABM, BMI1, BMI2, TBM, FMA, SHA, AVX2, AVX512F, AVX512CD, AVX512ER, AVX512PF, AVX512BW, AVX512DQ, AVX512VL, AVX512IFMA, AVX512VBMI.

Compatibility modes for older incompatible processors: Knights Corner, Intel Larrabee, Cyrix, Geode, Centaur, X86/486.

X86-64 Disassembler.

Bug fixes in this version.

Issue #6. Wrong calculating jump adresses. Fixed.
Issue #5. Issue with 16-bit call instruction. Fixed.
Issue #4 . Licensing. Project is under MIT License.

Backwards compatible to 32 bit, and 16 bit.

Supports instructions sets: MMX, SSE, SSE2, SSE3, SSSE3, SSE4, SSE4a, SSE4.1, SSE4.2, SMX, VMX, AMD-V, Intel VT-x, AES, ADX, HLE, MPX, ABM, BMI1, BMI2, TBM, FMA, SHA, AVX2, AVX512F, AVX512CD, AVX512ER, AVX512PF, AVX512BW, AVX512DQ, AVX512VL, AVX512IFMA, AVX512VBMI.

Compatibility modes for older incompatible processors: Knights Corner, Intel Larrabee, Cyrix, Geode, Centaur, X86/486.

X86-64 Disassembler.

Backwards compatible to 32 bit, and 16 bit.

Supports instructions sets: MMX, SSE, SSE2, SSE3, SSSE3, SSE4, SSE4a, SSE4.1, SSE4.2, SMX, VMX, AMD-V, Intel VT-x, AES, ADX, HLE, MPX, ABM, BMI1, BMI2, TBM, FMA, SHA, AVX2, AVX512F, AVX512CD, AVX512ER, AVX512PF, AVX512BW, AVX512DQ, AVX512VL, AVX512IFMA, AVX512VBMI.

Compatibility modes for older incompatible processors: Knights Corner, Intel Larrabee, Cyrix, Geode, Centaur, X86/486.

X86-64 Disassembler.

Is now backwards compatible to 32 bit, and 16 bit. Also supports AVX512 now.

Supports instructions sets: MMX, SSE, SSE2, SSE3, SSSE3, SSE4, SSE4a, SSE4.1, SSE4.2, SMX, VMX, AMD-V, Intel VT-x, AES, ADX, HLE, MPX, ABM, BMI1, BMI2, TBM, FMA, SHA, AVX2, AVX512F, AVX512CD, AVX512ER, AVX512PF, AVX512BW, AVX512DQ, AVX512VL, AVX512IFMA, AVX512VBMI.

X86-64 Disassembler.

Supports MMX, SSE1, SSE2, SSE3, SSSE3, SSE4, SSE4a, SSE4.1, SSE4.2, SMX, VMX, AES, ADX, HLE, MPX instructions.

X86-64 Disassembler.

Supports SSE1, SSE2, SSE3 MMX, SMX, VMX, SSE4a instructions.

X86-64 Disassembler.

*Operation Disassemble format improved.
*Small SIB byte IMM read error fixed because Data variable was not given to the IMM function.
*does not support OpCode 0F hex for two byte instructions yet.

X86-64 Disassembler.

Float operations now Disassemble

*only does not support opcode 0F hex for two byte instructions