Got supervisor regressions to pass (no mmu)

src/main/scala/vexiiriscv/Param.scala

@@ -31,6 +31,7 @@ class ParamSimple(){
  var withLateAlu = false
  var withMul = true
  var withDiv = true
+ var privParam = PrivilegedParam.base
  var relaxedBranch = false
  var relaxedShift = false
  var relaxedSrc = false
@@ -40,8 +41,8 @@ class ParamSimple(){
  // Debug modifiers
  val debugParam = sys.env.getOrElse("VEXIIRISCV_DEBUG_PARAM", "0").toInt.toBoolean
  if(debugParam) {
- decoders = 1
- lanes = 1
+ decoders = 2
+ lanes = 2
  regFileSync = false
  withGShare = true
  withBtb = true
@@ -54,6 +55,8 @@ class ParamSimple(){
  relaxedShift = false
  relaxedSrc = true
  performanceCounters = 4
+ privParam.withSupervisor = true
+ privParam.withUser = true
  }
 
 
@@ -103,7 +106,7 @@ class ParamSimple(){
  val plugins = ArrayBuffer[Hostable]()
  if(withLateAlu) assert(allowBypassFrom == 0)
 
- plugins += new riscv.RiscvPlugin(xlen, rvc, hartCount)
+ plugins += new riscv.RiscvPlugin(xlen, hartCount)
  withMmu match {
  case false => plugins += new memory.StaticTranslationPlugin(32, ioRange, fetchRange)
  case true =>
@@ -210,7 +213,7 @@ class ParamSimple(){
  plugins += new CsrRamPlugin()
  plugins += new PerformanceCounterPlugin(additionalCounterCount = performanceCounters)
  plugins += new CsrAccessPlugin(early0, writeBackKey = if(lanes == 1) "lane0" else "lane1")
- plugins += new PrivilegedPlugin(PrivilegedParam.full, 0 until hartCount, trapAt = 2)
+ plugins += new PrivilegedPlugin(privParam, 0 until hartCount, trapAt = 2)
  plugins += new EnvPlugin(early0, executeAt = 0)
 
  if(withLateAlu) {

src/main/scala/vexiiriscv/execute/CsrRamPlugin.scala

@@ -5,6 +5,7 @@ import spinal.core.fiber.Handle
 import spinal.lib.logic.{DecodingSpec, Masked, Symplify}
 import spinal.lib.{misc, _}
 import spinal.lib.misc.plugin.FiberPlugin
+import vexiiriscv.Global
 import vexiiriscv.fetch.InitService
 import vexiiriscv.riscv.Riscv
 
@@ -29,6 +30,8 @@ class CsrRamPlugin extends FiberPlugin with CsrRamService with InitService {
  awaitBuild()
  csrLock.await()
 
+ assert(Global.HART_COUNT.get == 1, "In general, all csrram access done by other plugins assume 1 hart, need to be update")
+
  val read = ramReadPort(CsrRamService.priority.CSR)
  val write = ramWritePort(CsrRamService.priority.CSR)
  portRetainer.release()

src/main/scala/vexiiriscv/execute/CsrService.scala

@@ -127,6 +127,29 @@ trait CsrService {
 }
 
 class CsrHartApi(csrService: CsrService, hartId : Int){
+
+ def onWrite(csrFilter : Any, onlyOnFire : Boolean)(body : => Unit) = csrService.onWrite(csrFilter, onlyOnFire){
+ when(csrService.writingHartId(hartId)){ body }
+ }
+ def writeWhen[T <: Data](value: T, cond: Bool, csrId: Int, bitOffset: Int = 0): Unit = {
+ onWrite(csrId, true) {
+ when(cond) {
+ value.assignFromBits(csrService.onWriteBits(bitOffset, widthOf(value) bits))
+ }
+ }
+ }
+
+ def onReadToWrite(csrFilter: Any)(body: => Unit) = csrService.onReadToWrite(csrFilter) {
+ when(csrService.readingHartId(hartId)) {
+ body
+ }
+ }
+ def readToWrite[T <: Data](value: T, csrFilter: Any, bitOffset: Int = 0): Unit = {
+ onReadToWrite(csrFilter) {
+ csrService.onReadToWriteBits(bitOffset, widthOf(value) bits) := value.asBits
+ }
+ }
+
  def read[T <: Data](value: T, csrFilter: Any, bitOffset: Int = 0): Unit = {
  val converted = value match {
  case v: Bits => v
@@ -151,7 +174,15 @@ class CsrHartApi(csrService: CsrService, hartId : Int){
  write(value, csrId, bitOffset)
  }
 
+ def readWrite(csrId: Int, thats: (Int, Data)*): Unit = for (that <- thats) readWrite(that._2, csrId, that._1)
+ def write(csrId: Int, thats: (Int, Data)*): Unit = for (that <- thats) write(that._2, csrId, that._1)
+ def read(csrId: Int, thats: (Int, Data)*): Unit = for (that <- thats) read(that._2, csrId, that._1)
+
  class Csr(csrFilter : Any) extends Area{
+ def onWrite(onlyOnFire: Boolean)(body: => Unit) = CsrHartApi.this.onWrite(csrFilter, onlyOnFire) {
+ body
+ }
+
  def read[T <: Data](value: T, bitOffset: Int = 0): Unit = {
  CsrHartApi.this.read(value, csrFilter, bitOffset)
  }