cleaning

SpinalHDL · Jan 5, 2024 · cf265e7 · cf265e7
1 parent 14f0664
commit cf265e7
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Showing 2 changed files with 14 additions and 12 deletions.
diff --git a/src/main/scala/vexiiriscv/Param.scala b/src/main/scala/vexiiriscv/Param.scala
@@ -63,7 +63,7 @@ class ParamSimple(){
  def getName() : String = {
  def opt(that : Boolean, v : String) = that.mux(v, "")
  val r = new ArrayBuffer[String]()
- r += s"rv${xlen}im"
+ r += s"rv${xlen}im${privParam.withSupervisor.mux("s","")}${privParam.withUser.mux("u","")}"
  r += s"d${decoders}"
  r += s"l${lanes}"
  r += regFileSync.mux("rfs","rfa")
@@ -90,6 +90,8 @@ class ParamSimple(){
  opt[Unit]("relaxed-src") action { (v, c) => relaxedSrc = true }
  opt[Unit]("with-mul") action { (v, c) => withMul = true }
  opt[Unit]("with-div") action { (v, c) => withDiv = true }
+ opt[Unit]("with-supervisor") action { (v, c) => privParam.withSupervisor = true; privParam.withUser = true }
+ opt[Unit]("with-user") action { (v, c) => privParam.withUser = true }
  opt[Unit]("without-mul") action { (v, c) => withMul = false }
  opt[Unit]("without-div") action { (v, c) => withDiv = false }
  opt[Unit]("with-gshare") action { (v, c) => withGShare = true }

diff --git a/src/main/scala/vexiiriscv/misc/PrivilegedPlugin.scala b/src/main/scala/vexiiriscv/misc/PrivilegedPlugin.scala
@@ -344,11 +344,6 @@ class PrivilegedPlugin(val p : PrivilegedParam, hartIds : Seq[Int], trapAt : Int
  }
  }
 
- // Implement read-only CSR space
- when(cap.onDecodeWrite && cap.onDecodeAddress(11 downto 10) === U"11") {
- cap.onDecodeTrap()
- }
-
  val defaultTrap = new Area {
  val csrPrivilege = cap.onDecodeAddress(8, 2 bits)
  val csrReadOnly = cap.onDecodeAddress(10, 2 bits) === U"11"
@@ -357,15 +352,19 @@ class PrivilegedPlugin(val p : PrivilegedParam, hartIds : Seq[Int], trapAt : Int
  }
  }
 
-
- val tvecFilter = CsrListFilter(List(CSR.MTVEC) ++ p.withSupervisor.option(CSR.STVEC))
- val epcFilter = CsrListFilter(List(CSR.MEPC) ++ p.withSupervisor.option(CSR.SEPC))
- cap.onWrite(tvecFilter, false) {cap.onWriteBits(0, 2 bits) := 0}
- cap.onWrite(epcFilter, false) {cap.onWriteBits(0, log2Up(Fetch.SLICE_BYTES) bits) := 0}
+ val readAnyWriteLegal = new Area {
+ val tvecFilter = CsrListFilter(List(CSR.MTVEC) ++ p.withSupervisor.option(CSR.STVEC))
+ val epcFilter = CsrListFilter(List(CSR.MEPC) ++ p.withSupervisor.option(CSR.SEPC))
+ cap.onWrite(tvecFilter, false) {
+ cap.onWriteBits(0, 2 bits) := 0
+ }
+ cap.onWrite(epcFilter, false) {
+ cap.onWriteBits(0, log2Up(Fetch.SLICE_BYTES) bits) := 0
+ }
+ }
 
 
  ramRetainers.csr.release()
-
  trapLock.await()
 
  val harts = for(hartId <- 0 until HART_COUNT) yield new Area{
@@ -668,6 +667,7 @@ class PrivilegedPlugin(val p : PrivilegedParam, hartIds : Seq[Int], trapAt : Int
  }
  }
  }
+
  ramRetainers.port.release()
  buildBefore.release()
  }