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gowin: Himbaechel. Extend clock router #1208

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merged 2 commits into from
Sep 8, 2023
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@yrabbit yrabbit commented Sep 4, 2023

Now the clock router can place a buffer into the specified network, which divides the network into two parts: from the source to the buffer, routing occurs through any available PIPs, and after the buffer to the sink, only through a dedicated global clock network.

This is made specifically for the Tangnano20k where the external oscillator is soldered to a regular non-clock pin. But it can be used for other purposes, you just need to remember that the recipient must be a CLK input or output pin.

The port/network to set the buffer to is specified in the .CST file:

CLOCK_LOC "name" BUFG;

Now the clock router can place a buffer into the specified network,
which divides the network into two parts: from the source to the buffer,
routing occurs through any available PIPs, and after the buffer to the
sink, only through a dedicated global clock network.

This is made specifically for the Tangnano20k where the external
oscillator is soldered to a regular non-clock pin. But it can be used
for other purposes, you just need to remember that the recipient must be
a CLK input or output pin.

The port/network to set the buffer to is specified in the .CST file:

CLOCK_LOC "name" BUFG;

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
ctx->createCell(buf_name, id_BUFG);
CellInfo *buf_ci = ctx->cells.at(buf_name).get();
buf_ci->addInput(id_I);
auto s_net = std::make_unique<NetInfo>(ctx->idf("$PACKER_BUF_%s", net.first.c_str(ctx)));
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can you use ctx->createNet here?

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fixed

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
@gatecat gatecat merged commit 890d7f7 into YosysHQ:master Sep 8, 2023
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@yrabbit yrabbit deleted the clk-gw branch September 8, 2023 07:17
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2 participants