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Gowin. Add PLL pads. #1309

Merged
merged 2 commits into from
Apr 9, 2024
Merged

Gowin. Add PLL pads. #1309

merged 2 commits into from
Apr 9, 2024

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yrabbit
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@yrabbit yrabbit commented Apr 7, 2024

If the CLKIN input of the PLL is connected to a special pin, then it makes sense to try to place the PLL so that it uses a direct implicit non-switched connection to this pin.

The transfer of information about pins for various purposes has been implemented (clock input signal, feedback, etc), but so far only CLKIN is used.

If the CLKIN input of the PLL is connected to a special pin, then it
makes sense to try to place the PLL so that it uses a direct implicit
non-switched connection to this pin.

The transfer of information about pins for various purposes has been
implemented (clock input signal, feedback, etc), but so far only CLKIN
is used.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
if (ci.bel == BelId()) {
NetInfo *ni = ci.getPort(id_CLKIN);
if (ni && ni->driver.cell) {
BelId pll_bel = gwu.get_pll_bel(ni->driver.cell->bel, id_CLKIN_T);
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I think this code will fail in the get_pll_bel call if the driver is unplaced - say logic, or another PLL, or whatever - the test should probably be ni && ni->driver.cell && ni->driver.cell->bel != BelId()

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oh yes, you're right.

Do not search for pads if the signal source for the PLL is something
other than the IO pin - these are guaranteed to already be placed and
have a bound Bel.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
@gatecat gatecat merged commit d3b53d8 into YosysHQ:master Apr 9, 2024
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@yrabbit yrabbit deleted the pll-pads branch April 9, 2024 08:36
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2 participants