Regex-based pattern to consider certain modules as blackboxes #4024
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pidgeon777
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In my input verilog file I have a certain amount of modules, e.g.:
Let suppose that I want to define all modules starting with
yyy
as blackboxes. Actually I have to manually do this:Is there any
yosys
command/option, or any way in general, to automatically consider as blackboxes the modules whose name is identified by a pattern?Beta Was this translation helpful? Give feedback.
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