preserving FSM state names while exporting FSMs to .kiss2 format

[gkamendje]

I use SystemVerilog enums to define the states of my FSMs something like

typedef enum logic [3:0] {
START, 
...
RUN

} rx_state_t

And I use the following to extract the FSM into a .kiss2 file

~/tmp_compile/tools/install/yosys/bin/yosys -L yosys_mem_ctrl.log "-m systemverilog -p" "read_systemverilog -defer ../../rtl/mem_pkg_defs.sv  ../../rtl/mem_ctrl.sv ../../rtl/sync_counter.sv; read_systemverilog  -link  ; "proc; opt -nodffe -nosdff; fsm -norecode  -nomap;"" fsm_export -o ./mem_ctrl.kiss2"

I was wondering if there is a simple way to preserve FSM state names while exporting FSMs to a .kiss2 file assuming no recoding. Instead of

---------0-- s0 s0 000000000000000000000000001000
-------001-- s0 s0 000000000000000000000000001000
--------11-- s0 s15 000000000000000000000000001000

I would like to have something like

---------0-- START START 000000000000000000000000001000
-------001-- START START 000000000000000000000000001000
--------11-- START RUN 000000000000000000000000001000

This would make the resulting graph generated by dot more readable and the FSM fully documented.
I can certainly post-process the .kiss2 files but I guess Yosys offers a more elegant solution.
I am aware that this might not be possible given that the string representation of the states might not be passed to Yosys's internal format by the HDL frontend.

BTW: is there a way to include the input FSM inputs and outputs name in the generated .kiss2 file?