cannot synthesize latch?

[lacary]

I have a very simple piece of verilog code describing a latch:
always @ (clk or data) begin
if (~clk) latch<=data
end

after yosys synthesis, the netlist looks as below:
always @*
if(!clk) latch=data;

Suppose that this is very simple latch description, yosys should support this, anybody could give me some suggestion? thanks

[nakengelhardt]

This should work. What architecture are you targeting and what script are you using?

[lacary]

my test.v:
module test (input wire clk,
input wire data,
output wire clkg);
reg latch;
always @(clk or data) begin
if (~clk) latch<=data;
end

assign clkg=latch;
endmodule

my script:
read_verilog -sv test.v
synth -top test

dfflibmap -liberty sk130_liberty_file
abc -liberty sk130_liberty_file
clean
write_verilog test.vg

[nakengelhardt]

Your script is not mapping latches ($_DLATCH_*_ internal cells), which aren't handled by dfflibmap. So they remain unmapped and get exported by write_verilog using the architecture-independent description you see in the output.

To map latches you would use an architecture-specific techmap file (e.g. this) and use the commands

dfflegalize -cell $_DLATCH_?_ x
techmap -map latch_map_file.v

[lacary]

thanks for your prompt reply. works now, thanks

[lacary]

another question, for any liberty file(other than sky 130), there should be an architecture-specific techmap file? where can I find that?

[lacary]

seems that I need to write the techmap file for a given liberty?

[titan73]

@nakengelhardt Shouldn't this be done automatically from the liberty file as for dfflibmap? With the same function or a similar one?