How to synthesize logic gates with 3 or more inputs?

[mivuzz]

hi I've been using yosys for about a week now, and ive loved it, but admittedly there's been a relatively simple thing that i haven't figured out how to do

the way it is now it seems like read_verilog defaults to using multiple two input logic gates in cascade instead of a single one with the required number of inputs whenever there is an expression with three or more nodes in the source code

is there a way to change this? thank you in advance :D

[nakengelhardt]

What is your yosys script? Gates are created far downstream of read_verilog...

[mivuzz]

What is your yosys script?

Hi, here's a snippet

module full_adder(
    input a, b, cin,
    output sum, cout
);

assign sum = a ^ b ^ cin;
assign cout = (a & b) | (a & cin) | (b & cin);

endmodule

It's a pretty simple script, just for the sake of getting this working.
After that i run read_verilog full_adder.v and write_json full_adder.json in order to obtain the netlist.

Gates are created far downstream of read_verilog...

Does this mean I should be using another script or modify my source or commands in order to access what does create them?

[nakengelhardt]

Does this mean I should be using another script or modify my source or commands in order to access what does create them?

Yes, you need to use a synthesis script. read_verilog creates a partially-netlist, partially-behavioral incomplete internal netlist representation of the design. write_json writes the current state of the internal netlist representation to JSON format. You will need to actually run at minimum hierarchy -top <foo> to resolve the design hierarchy, and proc to get a fully structural netlist representation, before you can reliably call write_json at all (it only worked on accident because your test case does not have an always block, otherwise you would have gotten an error). At this stage you would have word-level internal operators being used, it is also just by accident that your input only had single-bit wires so those operators were only 1 bit wide.

Please read this walkthrough for an idea of all the steps involved in a synthesis flow. If you would like to map to a specific library of gates that includes 3-input operators, you need to provide such a library. The most common way is via a liberty file. Here is an example of a script to map to a liberty gate library. OpenRoad flow scripts has a more complex example.