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I'm trying to create a helper function that will take a users verilog file and splits the ports from vectors to single bits, and outputs it back to verilog. To test this i'm using the example file for 'up3down5'.
I'm trying to use splitnets without running proc beforehand so I can show the user that their input file has been modified in this way. However if the module contains any processes it asks for proc to be run beforehand and splitnets skips the module.
Would it be possible at all to restrict splitnets to just the selection? Any ideas for other workarounds are appreciated!
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Hi!
I'm trying to create a helper function that will take a users verilog file and splits the ports from vectors to single bits, and outputs it back to verilog. To test this i'm using the example file for 'up3down5'.
I'm trying to use splitnets without running proc beforehand so I can show the user that their input file has been modified in this way. However if the module contains any processes it asks for proc to be run beforehand and splitnets skips the module.
Would it be possible at all to restrict splitnets to just the selection? Any ideas for other workarounds are appreciated!
Many thanks,
Andrew
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