sta
command hangs on some designs
#4648
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This issue is pending verification and/or reproduction
sta
command hangs on some designs
#4648
Version
Yosys 0.45+240 (git sha1 b4fd8e7, clang++ 14.0.0-1ubuntu1.1 -fPIC -O3)
On which OS did this happen?
Linux
Reproduction Steps
run with hanging
yosys -m ghdl
ghdl faulty.vhd -e faulty
synth_ecp5
sta
run without hanging
Here is the file that was used for testing. After download rename it to faulty.vhd
faulty.vhd
When waiting for a longer period of time yosys starts printing the latest arrival time, followed by the same repeating messages indefinitely. (starting at line 1242)
faulty.log
Expected Behavior
The
sta
command should run for any synthesized design without going into an infinite loop.Actual Behavior
the
sta
command hangs when using it on a finite state machine where the state transition is dependent on a signal of another process. If the signals that controls the transition is coming form outside of the module thesta
command runs without any issue.The text was updated successfully, but these errors were encountered: