Yosys does not accept module port lists with .port_identifier

[ldoolitt]

Version

Yosys 0.46 (git sha1 e97731b, g++ 12.2.0-14 -fPIC -O3)

On which OS did this happen?

Linux

Reproduction Steps

cat > same_port.v << EOT
module same_port (.a(i), .b(i)); // Name 'i' is declared inside the
                    // module as a inout port. Names 'a' and 'b' are
                    // defined for port connections.
inout i;
wire i;
endmodule
EOT
yosys -p "read_verilog same_port.v"

Expected Behavior

No crash.
IEEE Std 1354-2001 Version C gives the following BNF:

port ::=
  [ port expression ]
  | .port_identifier([port_expression])

and the same_port.v example file above is straight from the standard, p.187,
with the last three lines to complete the picture.

Vivado and iverilog both handle this case correctly.

Actual Behavior

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2024  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.46 (git sha1 e97731b9d, g++ 12.2.0-14 -fPIC -O3)

-- Running command `read_verilog same_port.v' --

1. Executing Verilog-2005 frontend: same_port.v
Parsing Verilog input from `same_port.v' to AST representation.
same_port.v:1: ERROR: syntax error, unexpected TOK_ID, expecting '.'

[ldoolitt]

Verilator also fails this test.
See its issue 5588 verilator/verilator#5588