write_verilog does not replace bwmux instances

[7FM]

Version

0.46

On which OS did this happen?

Linux

Reproduction Steps

Read in CVA6 via the yosys-slang plugin and try to write it out again into a single verilog file... Not so easy to reproduce, I guess.

Expected Behavior

write_verilog should output code without internal cells.

Actual Behavior

The exported verilog code still contains bwmux cells. I have to manually run bwmuxmap before write_verilog to remove all internal cells.

[povik]

Small reproducer:

read_slang <<EOF
module top;
reg x, b;
reg [2:0] a;
reg [2:0] out;
always_comb begin
	out = a;
	out[x] = b;
end
endmodule
EOF
write_verilog netlist.v

[povik]

Just to make clear it is a write_verilog bug, there's this part in its documentation:

    -noexpr
        without this option all internal cells are converted to Verilog
        expressions.

[jix]

Using the code below in verilog_backend.cc ends up with the correct xprop behavior passing those tests, the downside is that this doesn't roundtrip back into a bwmux when using read_verilog, not sure if that's something we would want to guarantee.

	if (cell->type == ID($bwmux))
	{
		std::string func_name = cellname(cell);


		int width = cell->parameters[ID::WIDTH].as_int();
		f << stringf("%s" "function [%d:0] %s;\n", indent.c_str(), width-1, func_name.c_str());
		f << stringf("%s" "  input [%d:0] a;\n", indent.c_str(), width-1);
		f << stringf("%s" "  input [%d:0] b;\n", indent.c_str(), width-1);
		f << stringf("%s" "  input [%d:0] s;\n", indent.c_str(), width-1);
		f << stringf("%s" "  integer i;\n", indent.c_str());
		f << stringf("%s" "  for (i = 0; i < %d; i = i + 1)\n", indent.c_str(), width);
		f << stringf("%s" "    %s[i] = s[i] ? b[i] : a[i];\n", indent.c_str(), func_name.c_str());
		f << stringf("%s" "endfunction\n", indent.c_str());

		f << stringf("%s" "assign ", indent.c_str());
		dump_sigspec(f, cell->getPort(ID::Y));
		f << stringf(" = %s(", func_name.c_str());
		dump_sigspec(f, cell->getPort(ID::A));
		f << stringf(", ");
		dump_sigspec(f, cell->getPort(ID::B));
		f << stringf(", ");
		dump_sigspec(f, cell->getPort(ID::S));
		f << stringf(");\n");
		return true;
	}