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Enable Clock Invalidation (#2485) (#2487)
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Loosen restrictions on clocks to enable them to be connected to
DontCare, i.e., be invalidated.

Co-authored-by: Jack Koenig <koenig@sifive.com>
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Co-authored-by: Jack Koenig <koenig@sifive.com>
(cherry picked from commit 5d8a0c8)

Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
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mergify[bot] and seldridge authored Apr 15, 2022
1 parent efd4748 commit b187a0c
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Showing 2 changed files with 9 additions and 1 deletion.
2 changes: 1 addition & 1 deletion core/src/main/scala/chisel3/Clock.scala
Original file line number Diff line number Diff line change
Expand Up @@ -23,7 +23,7 @@ sealed class Clock(private[chisel3] val width: Width = Width(1)) extends Element

override def connect(that: Data)(implicit sourceInfo: SourceInfo, connectCompileOptions: CompileOptions): Unit =
that match {
case _: Clock => super.connect(that)(sourceInfo, connectCompileOptions)
case _: Clock | DontCare => super.connect(that)(sourceInfo, connectCompileOptions)
case _ => super.badConnect(that)(sourceInfo)
}

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8 changes: 8 additions & 0 deletions src/test/scala/chiselTests/InvalidateAPISpec.scala
Original file line number Diff line number Diff line change
Expand Up @@ -228,4 +228,12 @@ class InvalidateAPISpec extends ChiselPropSpec with Matchers with BackendCompila
val firrtlOutput = myGenerateFirrtl(new ModuleWithoutDontCare)
firrtlOutput should include("is invalid")
}

property("a clock should be able to be connected to a DontCare") {
class ClockConnectedToDontCare extends Module {
val foo = IO(Output(Clock()))
foo := DontCare
}
myGenerateFirrtl(new ClockConnectedToDontCare) should include("foo is invalid")
}
}

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