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Enable Clock Invalidation #2485

Merged
merged 1 commit into from
Apr 15, 2022
Merged

Enable Clock Invalidation #2485

merged 1 commit into from
Apr 15, 2022

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Loosen restrictions on clocks to enable them to be connected to
DontCare, i.e., be invalidated.

Co-authored-by: Jack Koenig koenig@sifive.com
Signed-off-by: Schuyler Eldridge schuyler.eldridge@sifive.com

Loosen restrictions on clocks to enable them to be connected to
DontCare, i.e., be invalidated.

Co-authored-by: Jack Koenig <koenig@sifive.com>
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
@seldridge seldridge added this to the 3.4.x milestone Apr 15, 2022
@seldridge seldridge added the Please Merge Accepted PRs that are ready to be merged. Useful when waiting on CI. label Apr 15, 2022
@mergify mergify bot merged commit 5d8a0c8 into master Apr 15, 2022
@mergify mergify bot deleted the dev/seldridge/invalidate-clocks branch April 15, 2022 19:01
mergify bot pushed a commit that referenced this pull request Apr 15, 2022
Loosen restrictions on clocks to enable them to be connected to
DontCare, i.e., be invalidated.

Co-authored-by: Jack Koenig <koenig@sifive.com>
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Co-authored-by: Jack Koenig <koenig@sifive.com>
(cherry picked from commit 5d8a0c8)

# Conflicts:
#	core/src/main/scala/chisel3/Clock.scala
mergify bot pushed a commit that referenced this pull request Apr 15, 2022
Loosen restrictions on clocks to enable them to be connected to
DontCare, i.e., be invalidated.

Co-authored-by: Jack Koenig <koenig@sifive.com>
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Co-authored-by: Jack Koenig <koenig@sifive.com>
(cherry picked from commit 5d8a0c8)
@mergify mergify bot added the Backported This PR has been backported label Apr 15, 2022
mergify bot added a commit that referenced this pull request Apr 15, 2022
Loosen restrictions on clocks to enable them to be connected to
DontCare, i.e., be invalidated.

Co-authored-by: Jack Koenig <koenig@sifive.com>
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Co-authored-by: Jack Koenig <koenig@sifive.com>
(cherry picked from commit 5d8a0c8)

Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
seldridge added a commit that referenced this pull request Apr 15, 2022
seldridge added a commit that referenced this pull request Apr 15, 2022
Loosen restrictions on clocks to enable them to be connected to
DontCare, i.e., be invalidated.

Co-authored-by: Jack Koenig <koenig@sifive.com>
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Co-authored-by: Jack Koenig <koenig@sifive.com>
(cherry picked from commit 5d8a0c8)

# Conflicts:
#	core/src/main/scala/chisel3/Clock.scala
mergify bot added a commit that referenced this pull request Apr 15, 2022
Loosen restrictions on clocks to enable them to be connected to
DontCare, i.e., be invalidated.

Co-authored-by: Jack Koenig <koenig@sifive.com>
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Co-authored-by: Jack Koenig <koenig@sifive.com>
(cherry picked from commit 5d8a0c8)

# Conflicts:
#	core/src/main/scala/chisel3/Clock.scala

Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
jackkoenig added a commit that referenced this pull request Feb 28, 2023
This fixes handling of signed modulus and removes some redundant work.
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3 participants