Add lexical scope checks to Assert, Assume and Printf

[adkian-sifive]

When passing a Printable to assert, assume or printf, the scope of where the Printable was constructed should be the same as where it is being referenced. This is currently not checked, which makes it possible to construct cases where invalid FIRRTL is generated. Specifically, if the Printable is constructed in an inner module and referenced from an outer module, the resulting FIRRTL can have references to objects like wires or temporaries that are local to the inner module.

For example, the following snippet

class InnerPrintable extends Module {
  val in = IO(Input(UInt(8.W)))
  val out = IO(Output(UInt(8.W)))

  val w = Wire(UInt(8.W))
  w := 255.U
  val p = p"$w"

  out := in
}

ChiselStage.emitChirrtl { 
  new Module {
    val mod = Module(new InnerPrintable)
    printf(mod.p)
  }
}

outputs the problematic FIRRTL printf

  module InnerPrintable:
    input clock : Clock
    ...

    wire w : UInt<8>
    w <= UInt<8>("hff")
    ...

module Outer_Anon :
    input clock : Clock
    ...

    node _T = bits(reset, 0, 0)
    node _T_1 = eq(_T, UInt<1>("h0"))
    when _T_1 : 
      printf(clock, UInt<1>("h1"), "%d", w) : printf

where the wire w internal to InnerPrintable is being accessed outside of its scope.

This PR adds checks to assert, assume and printf to ensure that the Builder scopes at Printable construction and reference are the same.

Contributor Checklist

• Did you add Scaladoc to every public function/method?
• Did you add at least one test demonstrating the PR?
• Did you delete any extraneous printlns/debugging code?
• Did you specify the type of improvement?
• Did you add appropriate documentation in docs/src?
• Did you state the API impact?
• Did you specify the code generation impact?
• Did you request a desired merge strategy?
• Did you add text to be included in the Release Notes for this change?

Type of Improvement

• bug fix

API Impact

N/A

Backend Code Generation Impact

Printfs, asserts and assumes will not be present in the generated Verilog if the Printable scopes are invalid.

Desired Merge Strategy

• Squash: The PR will be squashed and merged (choose this if you have no preference.

Release Notes

Printables (and other objects?) used in printf, assert and assume can now only be referenced in the scopes in which they were constructed

Reviewer Checklist (only modified by reviewer)

• Did you add the appropriate labels?
• Did you mark the proper milestone (Bug fix: 3.4.x, [small] API extension: 3.5.x, API modification or big change: 3.6.0)?
• Did you review?
• Did you check whether all relevant Contributor checkboxes have been checked?
• Did you do one of the following when ready to merge:
  • Squash: You/ the contributor Enable auto-merge (squash), clean up the commit message, and label with Please Merge.
  • Merge: Ensure that contributor has cleaned up their commit history, then merge with Create a merge commit.

[jackkoenig]

This is a great idea but the implementation needs to be more about checking the lexical scope of the individual Data within a Printable rather than of the Printable objects themselves.

[jackkoenig]

Code looks great, I have some style suggestions but the functionality is all there and looks great!

[jackkoenig]

LGTM!