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Add a label "chisel3_builtin" to ifElseFatal intrinsic #3912

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merged 1 commit into from
Mar 7, 2024

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@uenoku uenoku commented Mar 7, 2024

This is a follow-up to #3825.

MFC has attached a laebl "chisel3_builtin" to every ifElseFatal assertion. Usually a label on ifElseFatal is just ignored but the label is emitted when compiled with -emit-chisel-asserts-as-sva. So labels on assertions converted from ifElseFatal disappear due to #3825. This PR restores labels to preserve the old behavior.

Contributor Checklist

  • Did you add Scaladoc to every public function/method?
  • Did you add at least one test demonstrating the PR?
  • Did you delete any extraneous printlns/debugging code?
  • Did you specify the type of improvement?
  • Did you add appropriate documentation in docs/src?
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  • Did you add text to be included in the Release Notes for this change?

Type of Improvement

  • Backend code generation

Desired Merge Strategy

  • Squash: The PR will be squashed and merged (choose this if you have no preference).

Release Notes

Add a label "chisel3_builtin" to ifElseFatal intrinsic.

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  • Did you add the appropriate labels? (Select the most appropriate one based on the "Type of Improvement")
  • Did you mark the proper milestone (Bug fix: 3.6.x, 5.x, or 6.x depending on impact, API modification or big change: 7.0)?
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This is a follow-up to chipsalliance#3825.

MFC has attached a laebl "chisel3_builtin" to every ifElseFatal assertion.
Usually a label on ifElseFatal is just ignored but the label is emitted
when compiled with `-emit-chisel-asserts-as-sva`. So labels on assertions
converted from ifElseFatal disappear due to chipsalliance#3825. This PR restores labels
to preserve the old behavior.
@uenoku uenoku added Bugfix Fixes a bug, will be included in release notes Backend Code Generation Affects backend code generation, will be included in release notes labels Mar 7, 2024
@uenoku uenoku removed the Bugfix Fixes a bug, will be included in release notes label Mar 7, 2024
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LGTM! Thanks!

@dtzSiFive dtzSiFive added this to the 7.0 milestone Mar 7, 2024
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Marking 7.0 because the other PR was 7.0.

@dtzSiFive dtzSiFive merged commit 35d3b71 into chipsalliance:main Mar 7, 2024
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dtzSiFive added a commit that referenced this pull request Mar 7, 2024
dtzSiFive added a commit that referenced this pull request Mar 7, 2024
dtzSiFive added a commit to dtzSiFive/chisel3 that referenced this pull request Apr 17, 2024
Restore chipsalliance#3912 and chipsalliance#3825.
Use intrinsic expression instead of intrinsic module.

This reverts commit 347d82b.
dtzSiFive added a commit to dtzSiFive/chisel3 that referenced this pull request Apr 17, 2024
Restore chipsalliance#3912 and chipsalliance#3825.
Use intrinsic expression instead of intrinsic module.

This reverts commit 347d82b.
dtzSiFive added a commit that referenced this pull request Apr 24, 2024
Restore #3912 and #3825.
Use intrinsic expression instead of intrinsic module.

This reverts commit 347d82b.
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