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Add ifElseFatal intrinsics; use it for chisel3.assert emission #4001

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merged 2 commits into from
Apr 24, 2024

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@dtzSiFive dtzSiFive commented Apr 17, 2024

Restore #3912 and #3825.
Use intrinsic expression instead of intrinsic module.

This reverts commit 347d82b.

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Type of Improvement

  • Backend code generation

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Release Notes

Support circt_chisel_ifelsefatal intrinsics and use it for chisel3.assert emission.

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@dtzSiFive dtzSiFive added the Backend Code Generation Affects backend code generation, will be included in release notes label Apr 17, 2024
@dtzSiFive dtzSiFive added this to the 7.0 milestone Apr 17, 2024
Restore chipsalliance#3912 and chipsalliance#3825.
Use intrinsic expression instead of intrinsic module.

This reverts commit 347d82b.
@dtzSiFive dtzSiFive force-pushed the feature/verif-intrinsic-again branch from 520ab47 to e45a9e0 Compare April 17, 2024 21:44
@dtzSiFive dtzSiFive marked this pull request as ready for review April 17, 2024 21:45
@dtzSiFive dtzSiFive requested a review from uenoku April 17, 2024 21:45
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LGTM although we should follow up by restoring the labeling behavior.

Merge once you're confident that the old performance issue is fixed (I'm pretty sure it is but it's important to check!)

Comment on lines 461 to 472
{
val x5 = {
val x1 = chisel3.assert(1.U === 1.U)
val x2 = cover(foo =/= bar)
val x3 = chisel3.assume(foo =/= 123.U)
val x4 = printf("foo = %d\n", foo)
x1
x2
}
}
}
val chirrtl = ChiselStage.emitCHIRRTL(new Test)
(chirrtl should include).regex("assert.*: x5")
(chirrtl should include).regex("cover.*: x5_x2")
(chirrtl should include).regex("cover.*: x5")
(chirrtl should include).regex("assume.*: x5_x3")
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I know this PR is just a re-application of 2 previously reverted PRs so I'm not going to block on this issue (since it was in a PR I previously approved), but this is not ideal. We should be able to maintain the old label behavior, but it will probably require a new Printable that wraps the Assert() object that we return from chisel3.assert.

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Ah, so instead of "chisel3_builtin" being the label for all of these, they get the "valname"/name included that would previously be mixed in by putting it in the "optional name" (trailing ": asdf" this test checks for)?

Yes that seems rather useful!

So Printable would help get a friendly name available (that's not available when IntrinsicExpr apply is called) so we could append it to the label StringParam while converting to the FIRRTL IR object, thereabouts? Makes sense to me!

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FYI previous behavior was just dropping optional names (assert_ label in the test) emitted for assert op. chisel3_builtin was used regardless of optional names.

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So Printable would help get a friendly name available (that's not available when IntrinsicExpr apply is called) so we could append it to the label StringParam while converting to the FIRRTL IR object, thereabouts? Makes sense to me!

Exactly!

FYI previous behavior was just dropping optional names (assert_ label in the test) emitted for assert op. chisel3_builtin was used regardless of optional names.

Perhaps for these asserts in firtool, but the intent was always to try to replace printf-encoded with real asserts with reasonable label behavior. This has been used by ChiselTest users, we just never fully implemented it in firtool, nor for printf-encoded asserts, but we should.

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Merge once you're confident that the old performance issue is fixed (I'm pretty sure it is but it's important to check!)

Yes, it's MUCH better now! Smaller FIRRTL too (compared to printf encoding).

Going to sit on this for at least a bit though to test things more thoroughly re:heavy intrinsic (expression) usage, let's ensure this sticks best way can this time 😉 .

@dtzSiFive dtzSiFive merged commit 22e9d02 into chipsalliance:main Apr 24, 2024
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@dtzSiFive dtzSiFive deleted the feature/verif-intrinsic-again branch April 24, 2024 00:04
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3 participants