Merge remote-tracking branch 'origin/avoid-subsystem-implicit-clock' …

…into beu-interrupt-cdc-hcook

src/main/scala/devices/debug/Periphery.scala

@@ -13,6 +13,7 @@ import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.diplomaticobjectmodel.logicaltree.LogicalModuleTree
 import freechips.rocketchip.jtag._
 import freechips.rocketchip.util._
+import freechips.rocketchip.prci.{ClockSinkParameters, ClockSinkNode}
 import freechips.rocketchip.tilelink._
 
 /** Protocols used for communicating with external debugging tools */
@@ -74,6 +75,11 @@ trait HasPeripheryDebug { this: BaseSubsystem =>
 
   val debugCustomXbarOpt = p(DebugModuleKey).map(params => LazyModule( new DebugCustomXbar(outputRequiresInput = false)))
   val apbDebugNodeOpt = p(ExportDebug).apb.option(APBMasterNode(Seq(APBMasterPortParameters(Seq(APBMasterParameters("debugAPB"))))))
+  val debugTLDomainOpt = p(DebugModuleKey).map { _ =>
+    val domain = ClockSinkNode(Seq(ClockSinkParameters()))
+    domain := tlbus.fixedClockNode
+    domain
+  }
   val debugOpt = p(DebugModuleKey).map { params =>
     val debug = LazyModule(new TLDebugModule(tlbus.beatBytes))
 
@@ -101,8 +107,8 @@ trait HasPeripheryDebugModuleImp extends LazyModuleImp {
   val psd = IO(new PSDIO)
 
   val resetctrl = outer.debugOpt.map { outerdebug =>
-    outerdebug.module.io.tl_reset := reset
-    outerdebug.module.io.tl_clock := clock
+    outerdebug.module.io.tl_reset := outer.debugTLDomainOpt.get.in.head._1.reset
+    outerdebug.module.io.tl_clock := outer.debugTLDomainOpt.get.in.head._1.clock
     val resetctrl = IO(new ResetCtrlIO(outerdebug.dmOuter.dmOuter.intnode.edges.out.size))
     outerdebug.module.io.hartIsInReset := resetctrl.hartIsInReset
     resetctrl.hartResetReq.foreach { rcio => outerdebug.module.io.hartResetReq.foreach { rcdm => rcio := rcdm }}

src/main/scala/devices/tilelink/BootROM.scala

@@ -7,6 +7,7 @@ import freechips.rocketchip.config.{Field, Parameters}
 import freechips.rocketchip.subsystem.{BaseSubsystem, HierarchicalLocation, HasTiles, TLBusWrapperLocation}
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tilelink._
+import freechips.rocketchip.prci.{ClockSinkDomain}
 
 import java.nio.ByteBuffer
 import java.nio.file.{Files, Paths}
@@ -65,19 +66,22 @@ object BootROM {
     */
   def attach(params: BootROMParams, subsystem: BaseSubsystem with HasTiles, where: TLBusWrapperLocation)
             (implicit p: Parameters): TLROM = {
-    val cbus = subsystem.locateTLBusWrapper(where)
+    val tlbus = subsystem.locateTLBusWrapper(where)
+    val bootROMDomainWrapper = LazyModule(new ClockSinkDomain(take = None))
+    bootROMDomainWrapper.clockNode := tlbus.fixedClockNode
+
     val bootROMResetVectorSourceNode = BundleBridgeSource[UInt]()
     lazy val contents = {
       val romdata = Files.readAllBytes(Paths.get(params.contentFileName))
       val rom = ByteBuffer.wrap(romdata)
       rom.array() ++ subsystem.dtb.contents
     }
 
-    val bootrom = subsystem {
-      LazyModule(new TLROM(params.address, params.size, contents, true, cbus.beatBytes))
+    val bootrom = bootROMDomainWrapper {
+      LazyModule(new TLROM(params.address, params.size, contents, true, tlbus.beatBytes))
     }
 
-    bootrom.node := cbus.coupleTo("bootrom"){ TLFragmenter(cbus) := _ }
+    bootrom.node := tlbus.coupleTo("bootrom"){ TLFragmenter(tlbus) := _ }
     // Drive the `subsystem` reset vector to the `hang` address of this Boot ROM.
     subsystem.tileResetVectorNexusNode := bootROMResetVectorSourceNode
     InModuleBody {

src/main/scala/devices/tilelink/CLINT.scala

@@ -109,6 +109,14 @@ trait CanHavePeripheryCLINT { this: BaseSubsystem =>
     val clint = LazyModule(new CLINT(params, cbus.beatBytes))
     LogicalModuleTree.add(logicalTreeNode, clint.logicalTreeNode)
     clint.node := tlbus.coupleTo("clint") { TLFragmenter(tlbus) := _ }
+
+    // Override the implicit clock and reset -- could instead include a clockNode in the clint, and make it a RawModuleImp?
+    InModuleBody {
+      clint.module.clock := tlbus.module.clock
+      clint.module.reset := tlbus.module.reset
+    }
+
     clint
+
   }
 }

src/main/scala/devices/tilelink/Plic.scala

@@ -13,6 +13,7 @@ import freechips.rocketchip.tilelink._
 import freechips.rocketchip.interrupts._
 import freechips.rocketchip.util._
 import freechips.rocketchip.util.property._
+import freechips.rocketchip.prci.{ClockSinkDomain}
 import chisel3.internal.sourceinfo.SourceInfo
 import freechips.rocketchip.diplomaticobjectmodel.model._
 
@@ -349,9 +350,13 @@ class PLICFanIn(nDevices: Int, prioBits: Int) extends Module {
 trait CanHavePeripheryPLIC { this: BaseSubsystem =>
   val plicOpt  = p(PLICKey).map { params =>
     val tlbus = locateTLBusWrapper(p(PLICAttachKey).slaveWhere)
-    val plic = LazyModule(new TLPLIC(params, tlbus.beatBytes))
+    val plicDomainWrapper = LazyModule(new ClockSinkDomain(take = None))
+    plicDomainWrapper.clockNode := tlbus.fixedClockNode
+
+    val plic = plicDomainWrapper { LazyModule(new TLPLIC(params, tlbus.beatBytes)) }
     plic.node := tlbus.coupleTo("plic") { TLFragmenter(tlbus) := _ }
     plic.intnode :=* ibus.toPLIC
+
     plic
   }
 }

src/main/scala/prci/ClockGroup.scala

@@ -49,7 +49,7 @@ class ClockGroupAggregator(groupName: String)(implicit p: Parameters) extends La
     val (out, _) = node.out.unzip
     val outputs = out.flatMap(_.member.data)
 
-    require (node.in.size == 1)
+    require (node.in.size == 1, s"Aggregator for groupName: ${groupName} had ${node.in.size} inward edges instead of 1")
     require (in.head.member.size == outputs.size)
     in.head.member.data.zip(outputs).foreach { case (i, o) => o := i }
   }

src/main/scala/subsystem/BaseSubsystem.scala

@@ -82,6 +82,10 @@ abstract class BaseSubsystem(val location: HierarchicalLocation = InSubsystem)
   val sbus = tlBusWrapperLocationMap(SBUS)
   tlBusWrapperLocationMap.lift(SBUS).map { _.clockGroupNode := asyncClockGroupsNode }
 
+  // TODO: Preserve legacy implicit-clock behavior for IBUS for now. If binding
+  // a PLIC to the CBUS, ensure it is synchronously coupled to the SBUS.
+  ibus.clockNode := sbus.fixedClockNode
+
   // TODO deprecate these public members to see where users are manually hardcoding a particular bus that might actually not exist in a certain dynamic topology
   val pbus = tlBusWrapperLocationMap.lift(PBUS).getOrElse(sbus)
   val fbus = tlBusWrapperLocationMap.lift(FBUS).getOrElse(sbus)

src/main/scala/subsystem/InterruptBus.scala

@@ -6,12 +6,13 @@ import Chisel._
 import freechips.rocketchip.config.{Field, Parameters}
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.interrupts._
+import freechips.rocketchip.prci.{ClockSinkDomain}
 
 /** Collects interrupts from internal and external devices and feeds them into the PLIC */ 
-class InterruptBusWrapper(implicit p: Parameters) extends SimpleLazyModule with LazyScope with HasClockDomainCrossing {
+class InterruptBusWrapper(implicit p: Parameters) extends ClockSinkDomain {
   override def shouldBeInlined = true
-  val int_bus = LazyModule(new IntXbar)
-  private val int_in_xing = this.crossIn(int_bus.intnode)
+  val int_bus = LazyModule(new IntXbar)   // Interrupt crossbar
+  private val int_in_xing  = this.crossIn(int_bus.intnode)
   private val int_out_xing = this.crossOut(int_bus.intnode)
   def from(name: Option[String])(xing: ClockCrossingType) = int_in_xing(xing) :=* IntNameNode(name)
   def to(name: Option[String])(xing: ClockCrossingType) = IntNameNode(name) :*= int_out_xing(xing)

src/main/scala/subsystem/RTC.scala

@@ -12,15 +12,17 @@ trait HasRTCModuleImp extends LazyModuleImp {
   private val rtcFreq = outer.p(DTSTimebase)
   private val internalPeriod: BigInt = pbusFreq / rtcFreq
 
+  val pbus = outer.locateTLBusWrapper(PBUS)
   // check whether pbusFreq >= rtcFreq
   require(internalPeriod > 0)
   // check wehther the integer division is within 5% of the real division
   require((pbusFreq - rtcFreq * internalPeriod) * 100 / pbusFreq <= 5)
 
   // Use the static period to toggle the RTC
-  val (_, int_rtc_tick) = Counter(true.B, internalPeriod.toInt)
-
-  outer.clintOpt.foreach { clint =>
-    clint.module.io.rtcTick := int_rtc_tick
+  chisel3.withClockAndReset(pbus.module.clock, pbus.module.reset) {
+    val (_, int_rtc_tick) = Counter(true.B, internalPeriod.toInt)
+    outer.clintOpt.foreach { clint =>
+      clint.module.io.rtcTick := int_rtc_tick
+    }
   }
 }