Implement Zicond extension #3329

rewired-gh · 2023-04-23T13:33:18Z

Related issue:
Not an issue.

Type of change: feature request

Impact: API addition (no impact on existing code)

Development Phase: implementation

Release Notes

Only implemented Zicond extension for ALU module. Still need to implement Zicond extension for other modules such as ABLU in the future.

By default, this extension is disabled. (Please refer to useConditionalZero in RocketCoreParams)

Also, Instructions.scala was updated. Code generated by risv-opcodes with command EXTENSIONS="unratified/rv_zicond" make inst.chisel. Only new lines were added.

linux-foundation-easycla · 2023-04-23T13:33:21Z

The committers listed above are authorized under a signed CLA.

✅ login: rewired-gh / name: rewired (0815dba, f3e3ee8)

rewired-gh · 2023-04-23T13:39:06Z

/easycla

src/main/scala/tile/Core.scala

src/main/scala/rocket/IDecode.scala

src/main/scala/rocket/ALU.scala

ZenithalHourlyRate · 2023-04-23T16:53:11Z

You might try to test your code using riscv-arch-test as the reference model (riscv-software-src/riscv-isa-sim#1241) and tests (riscv-non-isa/riscv-arch-test#321) are available.

linux-foundation-easycla · 2023-04-24T09:21:05Z

The committers listed above are authorized under a signed CLA.

✅ login: rewired-gh / name: rewired (0815dba, f3e3ee8, 1cc0527)

rewired-gh · 2023-04-24T09:29:40Z

I'm sorry for the force push. It was because the email address of the previous commit was mistyped and could not pass EasyCLA.

ZenithalHourlyRate

Other parts are fine to me now.

From private communication, it seems that it is not mature enough to add arch-test CI on Zicond as that test PR has not been merged and the toolchain does not have the support for it.

Adding CI for Zicond might be put in another draft PR.

src/main/scala/rocket/ALU.scala

rewired-gh · 2023-04-25T06:33:38Z

As mentioned in

Other parts are fine to me now.

From private communication, it seems that it is not mature enough to add arch-test CI on Zicond as that test PR has not been merged and the toolchain does not have the support for it.

Adding CI for Zicond might be put in another draft PR.

So I've follow the instructions in README.md to debug the implementation with GDB. Here is the assembly code I used:

addi x2, x0, 12    # Non-zero
add x3, x0, x0     # Zero
.word 0b00001110001000010101001000110011 # czero.eqz x4, x2, x2 (x4 := x2)
.word 0b00001110001100010101001000110011 # czero.eqz x4, x2, x3 (x4 := 0)
.word 0b00001110001000010111001000110011 # czero.nez x4, x2, x2 (x4 := 0)
.word 0b00001110001100010111001000110011 # czero.nez x4, x2, x3 (x4 := x2)

And here are the related GDB commands and output:

(gdb) i r x2 x3 x4
x2             0xc                 0xc
x3             0x0                 0x0
x4             0xffffffffb5e85757  0xffffffffb5e85757
(gdb) stepi       
0x000000008000000a      13          add x3, x0, x0     # Zero
   0x0000000080000002 <entry+2>:        000001b3                add     gp,zero,zero
   0x0000000080000006 <entry+6>:        0e215233                .insn   4, 0x0e215233
=> 0x000000008000000a <entry+10>:       0e315233                .insn   4, 0x0e315233
   0x000000008000000e <entry+14>:       0e217233                .insn   4, 0x0e217233
   0x0000000080000012 <entry+18>:       0e317233                .insn   4, 0x0e317233
(gdb) i r x2 x3 x4
x2             0xc                 0xc
x3             0x0                 0x0
x4             0xc                 0xc
(gdb) stepi       
0x000000008000000e      13          add x3, x0, x0     # Zero
   0x0000000080000002 <entry+2>:        000001b3                add     gp,zero,zero
   0x0000000080000006 <entry+6>:        0e215233                .insn   4, 0x0e215233
   0x000000008000000a <entry+10>:       0e315233                .insn   4, 0x0e315233
=> 0x000000008000000e <entry+14>:       0e217233                .insn   4, 0x0e217233
   0x0000000080000012 <entry+18>:       0e317233                .insn   4, 0x0e317233
(gdb) i r x2 x3 x4
x2             0xc                 0xc
x3             0x0                 0x0
x4             0x0                 0x0
(gdb) stepi       
0x0000000080000012      13          add x3, x0, x0     # Zero
   0x0000000080000002 <entry+2>:        000001b3                add     gp,zero,zero
   0x0000000080000006 <entry+6>:        0e215233                .insn   4, 0x0e215233
   0x000000008000000a <entry+10>:       0e315233                .insn   4, 0x0e315233
   0x000000008000000e <entry+14>:       0e217233                .insn   4, 0x0e217233
=> 0x0000000080000012 <entry+18>:       0e317233                .insn   4, 0x0e317233
(gdb) i r x2 x3 x4
x2             0xc                 0xc
x3             0x0                 0x0
x4             0x0                 0x0
(gdb) stepi       
18          nop
=> 0x0000000080000016 <entry+22>:       0001                    nop
(gdb) i r x2 x3 x4
x2             0xc                 0xc
x3             0x0                 0x0
x4             0xc                 0xc

It seems that everything worked as expected.

rewired-gh · 2023-04-26T08:39:46Z

The test for Zicond extension in riscv-non-isa/riscv-arch-test#321 is some generated assembly code. And it looks like this,

inst_607:
// rs1_val==-1431655765 and rs2_val==1431655766, 
// opcode: czero.eqz ; op1:x30; op2:x29; dest:x31; op1val:-0x55555555;  op2val:0x55555556
TEST_RR_OP(czero.eqz, x31, x30, x29, -0x55555555, -0x55555555, 0x55555556, x9, 71*XLEN/8, x10)

So we cannot directly substitute each line with binary instruction to make the test work. Since the latest RISC-V toolchain hasn't support Zicond extension, automated riscv-arch-test might not be possible, and putting CI in another drafted PR is not doable for now.

src/main/scala/tile/BaseTile.scala

ZenithalHourlyRate · 2023-05-07T04:17:44Z

@Mergifyio backport master

mergify · 2023-05-07T04:18:02Z

backport master

✅ Backports have been created

#3345 Implement Zicond extension (backport #3329) has been created for branch master

* Instructions: sync from riscv-opcodes (add zicond) * Zicond: implement czero.eqz, czero.nez * Zicond: fix implementation * Zicond: reduce code duplication * Add ISA extension when using Zicond * Fix ISA extensions ordering (cherry picked from commit 62162c5)

Implement Zicond extension (backport #3329)

* bump to Chisel 3.5.6 (#3222) * Remove deprecated code for BarrelShifter Cherry-picked chipsalliance/chisel@7372c9e Should use BarrelShifter from chisel3.std, but it is not published, see chipsalliance/chisel#2997 * Fix scala reflect error scala.reflect.internal.Types: constructor RecordMap in class RecordMap cannot be accessed in package util from package util in package rocketchip * explicit add legacy connect operators * replace all cde dependencies. * change api-config to cde in build.sbt * bump cde submodule * fix Makefile * IDecode: Fix aes64ks1i imm decode It is not rs2, it is imm Related to #3255 * CryptoNIST: refactor rnum This removes a redundant port As rnum is encoded in rs2 as imm now, we can get it just from rs2 * Remove redundant TLBExceptions V bit This was introduced by "(185cac8) Add hypervisor extension (#2841)" This is a dead code, as no circuit is producing and consuming this bit. This was discovered when migrating Core.scala to chisel3, where strict checking was applied for IO and firrtl found this is not connected. In the context of hypervisor extension, V bit, or _virtualization mode_, indicates whether the hart is currently executing in a guest. For TLBReq, the V bit is needed as it affects the PTW thus TLB behavior on whether to do _Two-Stage Address Translation_. However, the bit is not needed for TLBException. The exceptions (pf, gf, ae, ma) have no V=1/V=0 variants. Also, there is no point to add V bit for gf (guest page fault). The io.resp.gf added below in the original patch also does not connect io.resp.gf.v. If this V bit should be added for this specific exception, it should be connected. I assume this was added accidentally, as the original "extends CoreBundle()(p)" modification seems irrelevant. * update build system for cde bump * Fix unconnected io.start for TLRAMXbarTest and TLMulticlientXbarTest (cherry picked from commit 34d7309) * Fold HasPeripheryDebugModuleImp into HasPeripheryDebug (cherry picked from commit a2682ca) * Move HasDebugModule out of TileContextType (cherry picked from commit 0e4af6d) * Pinning nix to 2.13.3 in github workflows Nix 2.14 released with incompatibilities with cachix/install-nix-action. This PR pins nix to 2.13.3 to avoid CI fails See: cachix/install-nix-action#161 (cherry picked from commit 84533ae) * L1TLB: VS-mode SFENCE misses tera/giga-page entries fragmented superpages (#3297) (cherry picked from commit 8b52a6f) * feat: port Chisel2 to Chisel3 devices/ (cherry picked from commit 1ff0db3) * fix: add `chiselTypeOf` when inst Wire(in.d) (cherry picked from commit e645d94) * feat: port Chisel2 to Chisel3 rocket/ (cherry picked from commit d6a982b) * feat: port Chisel2 to Chisel3 amba/ (cherry picked from commit b2fd991) * Fix CharCount RoCC example bug Reset recv_beat (cherry picked from commit f19a90a) * Change CharCountRoCC Example to use dcacheParams RoCC accesses D$, not I$ (cherry picked from commit 61ea81c) * mill: fix empty cross arg for riscv-tests.Suite riscv-tests.suite[] wont compile (cherry picked from commit d86c011) * Hypervisor: encodeVirtualAddress extra MSB to canonicalize VS-disabled (#3314) (cherry picked from commit 0504a9b) * Support devOverride for diplomatic SRAMs (cherry picked from commit 12e21a6) * Support overriding the DTS node for diplomatic SRAMs (cherry picked from commit c8edec3) * Fix no-debug-node designs (cherry picked from commit 3b8d3c1) * all isaDTS strings to lowercase (#3333) (#3334) (cherry picked from commit 58c8249) Co-authored-by: Yangyu Chen <cyy@cyyself.name> * Deprecate old BusWrapper methods (#3337) (#3340) (cherry picked from commit 2570db7) Co-authored-by: Jerry Zhao <jerryz123@berkeley.edu> * Fix AXI4 RegisterRouter on Wire Clone (#3341) In legacy code it is ok to clone a Wire using Wire() now the requirement is more strict and WireDefault is needed Related to #3059 The Output is added for code style consistency Closes #3324 (cherry picked from commit fb5d7d0) Co-authored-by: Zenithal <i@zenithal.me> * Support TLFilter.mSubtract with multiple AddressSets (#3339) (#3343) Enables filtering out multiple ranges at once. (cherry picked from commit 4110563) Co-authored-by: Jerry Zhao <jerryz123@berkeley.edu> * Improve boundaryBuffers API | move boundaryBuffers to within-Tile (#3342) (#3344) * Add API to force TLBuffers into RocketTile as boundaryBuffers * Generate boundaryBuffers within the Tile, not the TilePRCIDomain (cherry picked from commit 3f74d79) Co-authored-by: Jerry Zhao <jerryz123@berkeley.edu> * Implement Zicond extension (#3329) * Instructions: sync from riscv-opcodes (add zicond) * Zicond: implement czero.eqz, czero.nez * Zicond: fix implementation * Zicond: reduce code duplication * Add ISA extension when using Zicond * Fix ISA extensions ordering (cherry picked from commit 62162c5) * feat: port Chisel2 to Chisel3 tilelink/ (cherry picked from commit 6c23100) * fix: not fully initialized wires in Edge.scala + using `DontCare` (cherry picked from commit 3902497) * fix: add chiselTypeOf when inst Wire + in.d and out.a; (cherry picked from commit e52773e) * fix: not fully initialized wires in Edge.scala + using `DontCare` (cherry picked from commit 5f7278b) * Revert to old := connects instead of :#= * Support removing the nonstandard CEASE from rocket (cherry picked from commit 956a1ff) * fix: Chisel3 #2944 Move SourceInfo to package experimental * Update debug_rom.S (cherry picked from commit a9ae0b9) * Update debug_rom_nonzero.S (cherry picked from commit 6ba9437) * Remove cloneType Ref to #2889 * Bump hardfloat * Bump to chisel3.6 * Switch to json4s-native * Update HeterogeneousBag to chisel3.6 * Bump mill flow to chisel 3.6.0 * Switch HeterogeneousBag to VectorMap * Update src/main/scala/util/HeterogeneousBag.scala Co-authored-by: Jack Koenig <koenig@sifive.com> * support circt and bump to 3.6 * Generalize Vec[TracedInstruction] to a TraceBundle (cherry picked from commit 85aca71) * Add time to TraceBundle (cherry picked from commit 57af718) * Supporting adding custom stuff to TraceBundle (cherry picked from commit f6f59c1) * Fix BlockableTraceBundle (cherry picked from commit efa8337) * Bump nix toolchain version * Fix TLSourceShrinker (cherry picked from commit d503368) * Support RoCC accels which define CSRs (#3358) (cherry picked from commit 7ddf02a) * Add support for an unsynthesizable ROB to produce a TracedInstruction stream from Rocket with wdata (cherry picked from commit d6c09c9) # Conflicts: # src/main/scala/rocket/RocketCore.scala # src/main/scala/subsystem/Configs.scala * Fix memory leak in debug_rob (cherry picked from commit b3f391c) * Fix unittests (cherry picked from commit a806851) * Fix TL unittests (cherry picked from commit ecf08f5) * Support blockable credited interfaces (cherry picked from commit c8cf935) * Make AsyncQueue use Rawmodule (cherry picked from commit 8db7364) * Support dynamic credit count in senders for CreditedIO (cherry picked from commit 5a5c127) * Fix TLJbarTest (cherry picked from commit e76a4ea) * Add [m/s/h]envcfg CSRs to satisfy spec requirements (#3373) (cherry picked from commit 9967142) * fix: Werror match may not be exhaustive (#3268) (#3384) + add `case _` to make match be exhaustive (cherry picked from commit 05d9db7) Co-authored-by: SingularityKChen <chency_singularity@163.com> * fix: empty argument list (#3262) (#3386) + add `()` to those empty argument list function call; Auto-application to `()` is deprecated. Supply the empty argument list `()` explicitly to invoke method (cherry picked from commit 9b383c5) Co-authored-by: SingularityKChen <chency_singularity@163.com> * fix: bit extraction use .U.extract(i) (#3263) (#3385) + replace `.U(i)` with `.U.extract(i)` (cherry picked from commit 9a1dc2d) Co-authored-by: SingularityKChen <chency_singularity@163.com> * TLB: must_alloc swapped AMO Logical/Arithmetic (#3390) (cherry picked from commit dc275c4) Co-authored-by: John Ingalls <43973001+ingallsj@users.noreply.github.com> * TLB: vsstatus.SUM check should not apply to Stage-2 fault before Stage-1 response (#3393) (#3399) (cherry picked from commit 43e0af1) Co-authored-by: John Ingalls <43973001+ingallsj@users.noreply.github.com> * CSR: optionally set delegable hypervisor exceptions (#3401) Given that usingHypervisor is used to distinguish whether the hardware supports hypervisor extensions, we should use it for the delegable exceptions as well. (cherry picked from commit 026f4c9) * Enable WARL custom CSRs, long-latency CSR accesses (#3388) * Support setting custom CSRs from datapath * Support CSR stalls (cherry picked from commit 005c6db) * PTW: set ae_ptw for out-of-range non-leaf PTEs (#3407) (#3410) For PTEs whose physical address is out-of-range, we need to set `ae_ptw` instead of `ae_final` to raise access-fault. Because non-leaf PTEs will not have R or X bits set, `ae_final` will be overrided by page-fault exceptions. (cherry picked from commit b8dad7f) Co-authored-by: Yinan Xu <xuyinan@ict.ac.cn> --------- Co-authored-by: Jiuyang Liu <liu@jiuyang.me> Co-authored-by: Zenithal <i@zenithal.me> Co-authored-by: Hansung Kim <hansung_kim@berkeley.edu> Co-authored-by: Liu Xiaoyi <circuitcoder0@gmail.com> Co-authored-by: John Ingalls <43973001+ingallsj@users.noreply.github.com> Co-authored-by: singularity <chency_singularity@163.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> Co-authored-by: Yangyu Chen <cyy@cyyself.name> Co-authored-by: rewired <39949564+rewired-gh@users.noreply.github.com> Co-authored-by: Jack Koenig <koenig@sifive.com> Co-authored-by: Yinan Xu <xuyinan@ict.ac.cn>

Instructions: sync from riscv-opcodes (add zicond)

0815dba

Zicond: implement czero.eqz, czero.nez

f3e3ee8

rewired-gh force-pushed the zicond_impl branch from 0f259ca to f3e3ee8 Compare April 23, 2023 13:43

ZenithalHourlyRate requested changes Apr 23, 2023

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Zicond: fix implementation

1cc0527

rewired-gh force-pushed the zicond_impl branch from a9fa53d to 1cc0527 Compare April 24, 2023 09:24

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Zicond: reduce code duplication

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rewired-gh and others added 2 commits April 26, 2023 20:52

Add ISA extension when using Zicond

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Merge branch 'dev' into zicond_impl

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rewired-gh requested a review from ZenithalHourlyRate April 28, 2023 16:54

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Inconsistency between AsciiDoc version and LaTeX version of unpriv spec riscv/riscv-isa-manual#1035

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Fix ISA extensions ordering

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rewired-gh requested a review from ZenithalHourlyRate May 6, 2023 04:00

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ZenithalHourlyRate merged commit 62162c5 into chipsalliance:dev May 7, 2023

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Implement Zicond extension (backport #3329) #3345

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jerryz123 added a commit that referenced this pull request May 8, 2023

Merge pull request #3345 from chipsalliance/mergify/bp/master/pr-3329

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Implement Zicond extension (backport #3329)

sequencer mentioned this pull request May 30, 2023

Remove SFC #3379

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Clean up all deprecations from chisel3p6 to embrace chisel5 #3392

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Implement Zicond extension #3329

Implement Zicond extension #3329

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Implement Zicond extension #3329

Implement Zicond extension #3329

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✅ Backports have been created

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