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See https://www.sifive.com/documentation, please update to latest TileLink Spec.(CMO in Hint) |
OceanS2000
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sequencer
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Feb 15, 2023
OceanS2000
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OceanS2000
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| val mask = RegInit(((BigInt(1) << width) - 1).U(width - 1, 0)) | ||
| val filter = Cat(scanRightOr(valid & ~mask), valid) | ||
| val unready = (filter >> 1).asUInt | (mask << width).asUInt | ||
| val readys = (~((unready >> width).asUInt & unready(width - 1, 0))).asUInt |
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No need to .asUInt here, this actually is a IDEA bug.
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tilelink/src/bundle/TLLink.scala
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| import scala.collection.immutable.SeqMap | ||
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| object TLLink { |
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maybe this should be a utils object
sequencer
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Feb 16, 2023
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| import chisel3.util.log2Ceil | ||
| import upickle.default.{macroRW, readwriter, ReadWriter => RW} | ||
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We do need ScalaDoc for this file!
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Initial implementation of TileLink bus arbiter and crossbar.