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[Arm64] AddAcross MaxAcross MinAcross MaxNumber MaxNumberPairwise MaxPairwise #32620

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merged 53 commits into from
Feb 21, 2020
Merged

[Arm64] AddAcross MaxAcross MinAcross MaxNumber MaxNumberPairwise MaxPairwise #32620

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ff93898
Add "MaxAcross" in AdvSimd.cs AdvSimd.PlatformNotSupported.cs
echesakov Feb 7, 2020
4a9c400
Add "MinAcross" in AdvSimd.cs AdvSimd.PlatformNotSupported.cs
echesakov Feb 7, 2020
cae0066
Update "AddAcross" in AdvSimd.cs AdvSimd.PlatformNotSupported.cs
echesakov Feb 7, 2020
9b13e23
Add "AddPairwise" and "AddPairwiseScalar" in AdvSimd.cs AdvSimd.Platf…
echesakov Feb 19, 2020
6dcee66
Add "MaxPairwise" and "MaxPairwiseScalar" in AdvSimd.cs AdvSimd.Platf…
echesakov Feb 19, 2020
8748dda
Add "MinPairwise" and "MinPairwiseScalar" in AdvSimd.cs AdvSimd.Platf…
echesakov Feb 19, 2020
3bcdd50
Add "MaxNumber" and "MaxNumberScalar" in AdvSimd.cs AdvSimd.PlatformN…
echesakov Feb 19, 2020
32380ad
Add "MaxNumberPairwise" and "MaxNumberPairwiseScalar" in AdvSimd.cs A…
echesakov Feb 19, 2020
7128c88
Add "MinNumber" and "MinNumberScalar" in AdvSimd.cs AdvSimd.PlatformN…
echesakov Feb 19, 2020
c285661
Add "MinNumberPairwise" and "MinNumberPairwiseScalar" in AdvSimd.cs A…
echesakov Feb 19, 2020
a3c2767
Add "MinNumberAcross" in AdvSimd.cs AdvSimd.PlatformNotSupported.cs
echesakov Feb 19, 2020
b5931c6
Add "MaxNumberAcross" in AdvSimd.cs AdvSimd.PlatformNotSupported.cs
echesakov Feb 19, 2020
ad52b4f
Update System.Runtime.Intrinsics.Experimental.cs
echesakov Feb 19, 2020
7391ecd
Precedence of BaseTypeFromFirstArg, BaseTypeFromSecondArg over "retur…
echesakov Feb 19, 2020
74f3776
Fix comment in instrsarm64.h
echesakov Feb 20, 2020
a75ec58
Datasize = 16 bytes for fmaxnmv, fmaxv, fminnv, fminv in emitarm64.cpp
echesakov Feb 19, 2020
58eba4a
Datasize = 8 bytes or 16 bytes for faddp, fmaxnmp, fmaxp, fminp, fmin…
echesakov Feb 20, 2020
c19b26e
Datasize = 16 bytes for addp in emitarm64.cpp
echesakov Feb 20, 2020
e89d6af
Update usages of faddp instruction in CodeGen::genSIMDIntrinsicDotPro…
echesakov Feb 19, 2020
a115435
Use DV_2T encoding form for addv, saddlv, smaxv, sminv, uaddlv, umaxv…
echesakov Feb 20, 2020
b22616e
Share IF_DV_2A and IF_DV_2R in emitter::emitOutputInstr in emitarm64.cpp
echesakov Feb 20, 2020
4abd134
Fix formatting in emitarm64.cpp
echesakov Feb 20, 2020
b0f9e03
Update "AddAcross" in hwintrinsiclistarm64.h
echesakov Feb 19, 2020
fbea4f0
Add "MaxAcross" and "MinAcross" in hwintrinsiclistarm64.h
echesakov Feb 10, 2020
d03e744
Add "AddPairwise" and "AddPairwiseScalar" in hwintrinsiclistarm64.h
echesakov Feb 19, 2020
4a0d153
Add "MaxPairwise" and "MaxPairwiseScalar" in hwintrinsiclistarm64.h
echesakov Feb 19, 2020
dd1fe99
Add "MinPairwise" and "MinPairwiseScalar" in hwintrinsiclistarm64.h
echesakov Feb 19, 2020
c70d14b
Order methods alphabetically in hwintrinsiclistarm64.h
echesakov Feb 10, 2020
2b7f289
Add "MaxNumber" and "MaxNumberScalar" in hwintrinsiclistarm64.h
echesakov Feb 19, 2020
6efbbbc
Add "MinNumber" and "MinNumberScalar" in hwintrinsiclistarm64.h
echesakov Feb 19, 2020
62de9f7
Add "MaxNumberPairwise" and "MaxNumberPairwiseScalar" in hwintrinsicl…
echesakov Feb 19, 2020
140d435
Add "MinNumberPairwise" and "MinNumberPairwiseScalar" in hwintrinsicl…
echesakov Feb 19, 2020
e8f2ad2
Add "MaxNumberAcross" in hwintrinsiclistarm64.h
echesakov Feb 19, 2020
bb14f72
Add "MinNumberAcross" in hwintrinsiclistarm64.h
echesakov Feb 19, 2020
405fc6f
Update CodeGen::genArm64EmitterUnitTests() in codegenarm64.cpp
echesakov Feb 19, 2020
07eb50b
Update "AddAcross" in GenerateTests.csx
echesakov Feb 15, 2020
7a80cbf
Add "MaxAcross" in GenerateTests.csx
echesakov Feb 15, 2020
3ca6980
Add "MinAcross" in GenerateTests.csx
echesakov Feb 15, 2020
c91cd6a
Add "MaxNumber" and "MaxNumberScalar" in GenerateTests.csx
echesakov Feb 15, 2020
9c663bd
Add "MinNumber" and "MinNumberScalar" in GenerateTests.csx
echesakov Feb 15, 2020
2b4ade6
Add "MaxNumberAcross" and "MinNumberAcross" in GenerateTests.csx
echesakov Feb 19, 2020
7fe0318
Add "AddPairwise" in AdvSimd in GenerateTests.csx
echesakov Feb 20, 2020
7cbef4d
Add "AddPairwise" and "AddPairwiseScalar" in AdvSimd.Arm64 in Generat…
echesakov Feb 20, 2020
dfb70f8
Add "MaxPairwise" in AdvSimd in GenerateTests.csx
echesakov Feb 20, 2020
0573dec
Add "MaxPairwise" and "MaxPairwiseScalar" in AdvSimd.Arm64 in Generat…
echesakov Feb 20, 2020
54724f7
Add "MinPairwise" in AdvSimd in GenerateTests.csx
echesakov Feb 20, 2020
82de0d1
Add "MinPairwise" and "MinPairwiseScalar" in AdvSimd.Arm64 in Generat…
echesakov Feb 20, 2020
808a55d
Add "MaxNumberPairwise" and "MaxNumberPairwiseScalar" in AdvSimd.Arm6…
echesakov Feb 20, 2020
9acbc2c
Add "MinNumberPairwise" and "MinNumberPairwiseScalar" in AdvSimd.Arm6…
echesakov Feb 20, 2020
b4d77d5
Update Helpers.cs Helpers.tt
echesakov Feb 15, 2020
737288a
Update AdvSimd/ AdvSimd.Arm64/
echesakov Feb 20, 2020
e096445
Remove whitespace in _BinaryOpTestTemplate.template _TernaryOpTestTem…
echesakov Feb 20, 2020
28d9648
Update AdvSimd/ AdvSimd.Arm64/
echesakov Feb 20, 2020
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41 changes: 19 additions & 22 deletions src/coreclr/src/jit/codegenarm64.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -4516,13 +4516,13 @@ void CodeGen::genSIMDIntrinsicDotProduct(GenTreeSIMD* simdNode)
{
if (opt == INS_OPTS_4S)
{
GetEmitter()->emitIns_R_R_R(INS_faddp, attr, tmpReg, tmpReg, tmpReg, INS_OPTS_4S);
GetEmitter()->emitIns_R_R_R(INS_faddp, EA_16BYTE, tmpReg, tmpReg, tmpReg, INS_OPTS_4S);
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These are just changing the size from element to vector right?

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Exactly - my previous change #32277 that did the opposite for faddp (i.e. changing the size from vector to element) was breaking consistency with other part of the JIT and I am rolling it back here.

}
GetEmitter()->emitIns_R_R(INS_faddp, EA_4BYTE, targetReg, tmpReg, INS_OPTS_2S);
GetEmitter()->emitIns_R_R(INS_faddp, EA_8BYTE, targetReg, tmpReg, INS_OPTS_2S);
}
else
{
GetEmitter()->emitIns_R_R(INS_faddp, EA_8BYTE, targetReg, tmpReg, INS_OPTS_2D);
GetEmitter()->emitIns_R_R(INS_faddp, EA_16BYTE, targetReg, tmpReg, INS_OPTS_2D);
}
}
else
Expand Down Expand Up @@ -6893,32 +6893,32 @@ void CodeGen::genArm64EmitterUnitTests()
theEmitter->emitIns_R_R(INS_fabs, EA_16BYTE, REG_V8, REG_V9, INS_OPTS_2D);

// fmaxp scalar
theEmitter->emitIns_R_R(INS_fmaxp, EA_4BYTE, REG_V0, REG_V1, INS_OPTS_2S);
theEmitter->emitIns_R_R(INS_fmaxp, EA_8BYTE, REG_V2, REG_V3, INS_OPTS_2D);
theEmitter->emitIns_R_R(INS_fmaxp, EA_8BYTE, REG_V0, REG_V1, INS_OPTS_2S);
theEmitter->emitIns_R_R(INS_fmaxp, EA_16BYTE, REG_V2, REG_V3, INS_OPTS_2D);

// fmaxnmp scalar
theEmitter->emitIns_R_R(INS_fmaxnmp, EA_4BYTE, REG_V0, REG_V1, INS_OPTS_2S);
theEmitter->emitIns_R_R(INS_fmaxnmp, EA_8BYTE, REG_V2, REG_V3, INS_OPTS_2D);
theEmitter->emitIns_R_R(INS_fmaxnmp, EA_8BYTE, REG_V0, REG_V1, INS_OPTS_2S);
theEmitter->emitIns_R_R(INS_fmaxnmp, EA_16BYTE, REG_V2, REG_V3, INS_OPTS_2D);

// fmaxnmv vector
theEmitter->emitIns_R_R(INS_fmaxnmv, EA_4BYTE, REG_V0, REG_V1, INS_OPTS_4S);
theEmitter->emitIns_R_R(INS_fmaxnmv, EA_16BYTE, REG_V0, REG_V1, INS_OPTS_4S);

// fmaxv vector
theEmitter->emitIns_R_R(INS_fmaxv, EA_4BYTE, REG_V0, REG_V1, INS_OPTS_4S);
theEmitter->emitIns_R_R(INS_fmaxv, EA_16BYTE, REG_V0, REG_V1, INS_OPTS_4S);

// fminp vector
theEmitter->emitIns_R_R(INS_fminp, EA_4BYTE, REG_V0, REG_V1, INS_OPTS_2S);
theEmitter->emitIns_R_R(INS_fminp, EA_8BYTE, REG_V2, REG_V3, INS_OPTS_2D);
// fminp scalar
theEmitter->emitIns_R_R(INS_fminp, EA_8BYTE, REG_V0, REG_V1, INS_OPTS_2S);
theEmitter->emitIns_R_R(INS_fminp, EA_16BYTE, REG_V2, REG_V3, INS_OPTS_2D);

// fminnmp scalar
theEmitter->emitIns_R_R(INS_fminnmp, EA_4BYTE, REG_V0, REG_V1, INS_OPTS_2S);
theEmitter->emitIns_R_R(INS_fminnmp, EA_8BYTE, REG_V2, REG_V3, INS_OPTS_2D);
theEmitter->emitIns_R_R(INS_fminnmp, EA_8BYTE, REG_V0, REG_V1, INS_OPTS_2S);
theEmitter->emitIns_R_R(INS_fminnmp, EA_16BYTE, REG_V2, REG_V3, INS_OPTS_2D);

// fminnmv vector
theEmitter->emitIns_R_R(INS_fminnmv, EA_4BYTE, REG_V0, REG_V1, INS_OPTS_4S);
theEmitter->emitIns_R_R(INS_fminnmv, EA_16BYTE, REG_V0, REG_V1, INS_OPTS_4S);

// fminv vector
theEmitter->emitIns_R_R(INS_fminv, EA_4BYTE, REG_V0, REG_V1, INS_OPTS_4S);
theEmitter->emitIns_R_R(INS_fminv, EA_16BYTE, REG_V0, REG_V1, INS_OPTS_4S);

// fneg scalar
theEmitter->emitIns_R_R(INS_fneg, EA_4BYTE, REG_V0, REG_V1);
Expand Down Expand Up @@ -7023,15 +7023,13 @@ void CodeGen::genArm64EmitterUnitTests()
theEmitter->emitIns_R_R(INS_addv, EA_16BYTE, REG_V6, REG_V7, INS_OPTS_16B);
theEmitter->emitIns_R_R(INS_addv, EA_8BYTE, REG_V8, REG_V9, INS_OPTS_4H);
theEmitter->emitIns_R_R(INS_addv, EA_16BYTE, REG_V10, REG_V11, INS_OPTS_8H);
theEmitter->emitIns_R_R(INS_addv, EA_8BYTE, REG_V12, REG_V13, INS_OPTS_2S);
theEmitter->emitIns_R_R(INS_addv, EA_16BYTE, REG_V14, REG_V15, INS_OPTS_4S);

// saddlv vector
theEmitter->emitIns_R_R(INS_saddlv, EA_8BYTE, REG_V4, REG_V5, INS_OPTS_8B);
theEmitter->emitIns_R_R(INS_saddlv, EA_16BYTE, REG_V6, REG_V7, INS_OPTS_16B);
theEmitter->emitIns_R_R(INS_saddlv, EA_8BYTE, REG_V8, REG_V9, INS_OPTS_4H);
theEmitter->emitIns_R_R(INS_saddlv, EA_16BYTE, REG_V10, REG_V11, INS_OPTS_8H);
theEmitter->emitIns_R_R(INS_saddlv, EA_8BYTE, REG_V12, REG_V13, INS_OPTS_2S);
theEmitter->emitIns_R_R(INS_saddlv, EA_16BYTE, REG_V14, REG_V15, INS_OPTS_4S);

// smaxv vector
Expand All @@ -7053,7 +7051,6 @@ void CodeGen::genArm64EmitterUnitTests()
theEmitter->emitIns_R_R(INS_uaddlv, EA_16BYTE, REG_V6, REG_V7, INS_OPTS_16B);
theEmitter->emitIns_R_R(INS_uaddlv, EA_8BYTE, REG_V8, REG_V9, INS_OPTS_4H);
theEmitter->emitIns_R_R(INS_uaddlv, EA_16BYTE, REG_V10, REG_V11, INS_OPTS_8H);
theEmitter->emitIns_R_R(INS_uaddlv, EA_8BYTE, REG_V12, REG_V13, INS_OPTS_2S);
theEmitter->emitIns_R_R(INS_uaddlv, EA_16BYTE, REG_V14, REG_V15, INS_OPTS_4S);

// umaxv vector
Expand All @@ -7071,8 +7068,8 @@ void CodeGen::genArm64EmitterUnitTests()
theEmitter->emitIns_R_R(INS_uminv, EA_16BYTE, REG_V12, REG_V13, INS_OPTS_4S);

// faddp scalar
theEmitter->emitIns_R_R(INS_faddp, EA_4BYTE, REG_V0, REG_V1, INS_OPTS_2S);
theEmitter->emitIns_R_R(INS_faddp, EA_8BYTE, REG_V2, REG_V3, INS_OPTS_2D);
theEmitter->emitIns_R_R(INS_faddp, EA_8BYTE, REG_V0, REG_V1, INS_OPTS_2S);
theEmitter->emitIns_R_R(INS_faddp, EA_16BYTE, REG_V2, REG_V3, INS_OPTS_2D);

// INS_fcvtl
theEmitter->emitIns_R_R(INS_fcvtl, EA_4BYTE, REG_V0, REG_V1);
Expand Down Expand Up @@ -7575,7 +7572,7 @@ void CodeGen::genArm64EmitterUnitTests()
theEmitter->emitIns_R_R_R(INS_add, EA_16BYTE, REG_V21, REG_V22, REG_V23, INS_OPTS_2D);

// addp
theEmitter->emitIns_R_R(INS_addp, EA_8BYTE, REG_V0, REG_V1, INS_OPTS_2D); // scalar 8BYTE
theEmitter->emitIns_R_R(INS_addp, EA_16BYTE, REG_V0, REG_V1, INS_OPTS_2D); // scalar 16BYTE
theEmitter->emitIns_R_R_R(INS_addp, EA_8BYTE, REG_V3, REG_V4, REG_V5, INS_OPTS_8B);
theEmitter->emitIns_R_R_R(INS_addp, EA_8BYTE, REG_V6, REG_V7, REG_V8, INS_OPTS_4H);
theEmitter->emitIns_R_R_R(INS_addp, EA_8BYTE, REG_V9, REG_V10, REG_V11, INS_OPTS_2S);
Expand Down
79 changes: 45 additions & 34 deletions src/coreclr/src/jit/emitarm64.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -732,33 +732,42 @@ void emitter::emitInsSanityCheck(instrDesc* id)

case IF_DV_2Q: // DV_2Q .........X...... ......nnnnnddddd Sd Vn (faddp, fmaxnmp, fmaxp, fminnmp,
// fminp - scalar)
if (id->idOpSize() == EA_8BYTE)
if (id->idOpSize() == EA_16BYTE)
{
assert(id->idInsOpt() == INS_OPTS_2D);
}
else
{
assert(id->idOpSize() == EA_4BYTE);
assert(id->idOpSize() == EA_8BYTE);
assert(id->idInsOpt() == INS_OPTS_2S);
}
assert(isVectorRegister(id->idReg1()));
assert(isVectorRegister(id->idReg2()));
break;

case IF_DV_2R: // DV_2R .Q.......X...... ......nnnnnddddd Sd Vn (fmaxnmv, fmaxv, fminnmv, fminv)
assert(id->idOpSize() == EA_4BYTE);
assert(id->idOpSize() == EA_16BYTE);
assert(id->idInsOpt() == INS_OPTS_4S);
assert(isVectorRegister(id->idReg1()));
assert(isVectorRegister(id->idReg2()));
break;

case IF_DV_2S: // DV_2S ........XX...... ......nnnnnddddd Sd Vn (addp - scalar)
assert(id->idOpSize() == EA_8BYTE);
assert(id->idOpSize() == EA_16BYTE);
assert(id->idInsOpt() == INS_OPTS_2D);
assert(isVectorRegister(id->idReg1()));
assert(isVectorRegister(id->idReg2()));
break;

case IF_DV_2T: // DV_2T .Q......XX...... ......nnnnnddddd Sd Vn (addv, saddlv, smaxv, sminv, uaddlv,
// umaxv, uminv)
assert(isValidVectorDatasize(id->idOpSize()));
elemsize = optGetElemsize(id->idInsOpt());
assert((elemsize != EA_8BYTE) && (id->idInsOpt() != INS_OPTS_2S)); // can't use 2D or 1D or 2S
assert(isVectorRegister(id->idReg1()));
assert(isVectorRegister(id->idReg2()));
break;

case IF_DV_3A: // DV_3A .Q......XX.mmmmm ......nnnnnddddd Vd Vn Vm (vector)
assert(isValidVectorDatasize(id->idOpSize()));
assert(isValidArrangement(id->idOpSize(), id->idInsOpt()));
Expand Down Expand Up @@ -2085,6 +2094,7 @@ emitter::code_t emitter::emitInsCode(instruction ins, insFormat fmt)
case IF_DV_2O:
case IF_DV_2P:
case IF_DV_2R:
case IF_DV_2T:
case IF_DV_3A:
case IF_DV_3AI:
case IF_DV_3B:
Expand Down Expand Up @@ -4071,6 +4081,14 @@ void emitter::emitIns_R_R(
case INS_uaddlv:
case INS_umaxv:
case INS_uminv:
assert(isVectorRegister(reg1));
assert(isVectorRegister(reg2));
assert(isValidVectorDatasize(size));
assert(isValidArrangement(size, opt));
assert((opt != INS_OPTS_2S) && (opt != INS_OPTS_1D) && (opt != INS_OPTS_2D)); // Reserved encodings
fmt = IF_DV_2T;
break;

case INS_rev64:
assert(isVectorRegister(reg1));
assert(isVectorRegister(reg2));
Expand Down Expand Up @@ -4345,7 +4363,7 @@ void emitter::emitIns_R_R(
case INS_fminnmp:
case INS_fminp:
// Scalar operation
assert(((size == EA_4BYTE) && (opt == INS_OPTS_2S)) || ((size == EA_8BYTE) && (opt == INS_OPTS_2D)));
assert(((size == EA_8BYTE) && (opt == INS_OPTS_2S)) || ((size == EA_16BYTE) && (opt == INS_OPTS_2D)));
assert(isVectorRegister(reg1));
assert(isVectorRegister(reg2));
fmt = IF_DV_2Q;
Expand All @@ -4355,15 +4373,15 @@ void emitter::emitIns_R_R(
case INS_fmaxv:
case INS_fminnmv:
case INS_fminv:
assert(size == EA_4BYTE);
assert(size == EA_16BYTE);
assert(opt == INS_OPTS_4S);
assert(isVectorRegister(reg1));
assert(isVectorRegister(reg2));
fmt = IF_DV_2R;
break;

case INS_addp:
assert(size == EA_8BYTE);
assert(size == EA_16BYTE);
assert(opt == INS_OPTS_2D);
assert(isVectorRegister(reg1));
assert(isVectorRegister(reg2));
Expand Down Expand Up @@ -10075,6 +10093,7 @@ size_t emitter::emitOutputInstr(insGroup* ig, instrDesc* id, BYTE** dp)
break;

case IF_DV_2A: // DV_2A .Q.......X...... ......nnnnnddddd Vd Vn (fabs, fcvt - vector)
case IF_DV_2R: // DV_2R .Q.......X...... ......nnnnnddddd Sd Vn (fmaxnmv, fmaxv, fminnmv, fminv)
elemsize = optGetElemsize(id->idInsOpt());
code = emitInsCode(ins, fmt);
code |= insEncodeVectorsize(id->idOpSize()); // Q
Expand Down Expand Up @@ -10156,8 +10175,6 @@ size_t emitter::emitOutputInstr(insGroup* ig, instrDesc* id, BYTE** dp)
break;

case IF_DV_2G: // DV_2G .........X...... ......nnnnnddddd Vd Vn (fmov, fcvtXX - register)
case IF_DV_2Q: // DV_2Q .........X...... ......nnnnnddddd Vd Vn (faddp, fmaxnmp, fmaxp, fminnmp,
// fminp - scalar)
elemsize = id->idOpSize();
code = emitInsCode(ins, fmt);
code |= insEncodeFloatElemsize(elemsize); // X
Expand Down Expand Up @@ -10202,7 +10219,6 @@ size_t emitter::emitOutputInstr(insGroup* ig, instrDesc* id, BYTE** dp)
break;

case IF_DV_2L: // DV_2L ........XX...... ......nnnnnddddd Vd Vn (abs, neg - scalar)
case IF_DV_2S: // DV_2S ........XX...... ......nnnnnddddd Sd Vn (addp - scalar)
elemsize = id->idOpSize();
code = emitInsCode(ins, fmt);
code |= insEncodeElemsize(elemsize); // XX
Expand All @@ -10212,6 +10228,8 @@ size_t emitter::emitOutputInstr(insGroup* ig, instrDesc* id, BYTE** dp)
break;

case IF_DV_2M: // DV_2M .Q......XX...... ......nnnnnddddd Vd Vn (abs, neg - vector)
case IF_DV_2T: // DV_2T .Q......XX...... ......nnnnnddddd Sd Vn (addv, saddlv, smaxv, sminv, uaddlv,
// umaxv, uminv)
elemsize = optGetElemsize(id->idInsOpt());
code = emitInsCode(ins, fmt);
code |= insEncodeVectorsize(id->idOpSize()); // Q
Expand Down Expand Up @@ -10249,17 +10267,25 @@ size_t emitter::emitOutputInstr(insGroup* ig, instrDesc* id, BYTE** dp)
dst += emitOutput_Instr(dst, code);
break;

case IF_DV_2R: // DV_2R .Q.......X...... ......nnnnnddddd Sd Vn (fmaxnmv, fmaxv, fminnmv, fminv)
code = emitInsCode(ins, fmt);
datasize = optGetDatasize(id->idInsOpt());
case IF_DV_2Q: // DV_2Q .........X...... ......nnnnnddddd Vd Vn (faddp, fmaxnmp, fmaxp, fminnmp,
// fminp - scalar)
elemsize = optGetElemsize(id->idInsOpt());
code |= insEncodeVectorsize(datasize); // Q
code = emitInsCode(ins, fmt);
code |= insEncodeFloatElemsize(elemsize); // X
code |= insEncodeReg_Vd(id->idReg1()); // ddddd
code |= insEncodeReg_Vn(id->idReg2()); // nnnnn
dst += emitOutput_Instr(dst, code);
break;

case IF_DV_2S: // DV_2S ........XX...... ......nnnnnddddd Sd Vn (addp - scalar)
elemsize = optGetElemsize(id->idInsOpt());
code = emitInsCode(ins, fmt);
code |= insEncodeElemsize(elemsize); // XX
code |= insEncodeReg_Vd(id->idReg1()); // ddddd
code |= insEncodeReg_Vn(id->idReg2()); // nnnnn
dst += emitOutput_Instr(dst, code);
break;

case IF_DV_3A: // DV_3A .Q......XX.mmmmm ......nnnnnddddd Vd Vn Vm (vector)
code = emitInsCode(ins, fmt);
elemsize = optGetElemsize(id->idInsOpt());
Expand Down Expand Up @@ -11672,25 +11698,8 @@ void emitter::emitDispIns(
break;

case IF_DV_2M: // DV_2M .Q......XX...... ......nnnnnddddd Vd Vn (abs, neg - vector)
switch (ins)
{
case INS_addv:
case INS_saddlv:
case INS_smaxv:
case INS_sminv:
case INS_uaddlv:
case INS_umaxv:
case INS_uminv:
elemsize = optGetElemsize(id->idInsOpt());
emitDispReg(id->idReg1(), elemsize, true);
emitDispVectorReg(id->idReg2(), id->idInsOpt(), false);
break;

default:
emitDispVectorReg(id->idReg1(), id->idInsOpt(), true);
emitDispVectorReg(id->idReg2(), id->idInsOpt(), false);
break;
}
emitDispVectorReg(id->idReg1(), id->idInsOpt(), true);
emitDispVectorReg(id->idReg2(), id->idInsOpt(), false);
break;

case IF_DV_2N: // DV_2N .........iiiiiii ......nnnnnddddd Vd Vn imm (shift - scalar)
Expand Down Expand Up @@ -11812,7 +11821,9 @@ void emitter::emitDispIns(
// fminp - scalar)
case IF_DV_2R: // DV_2R .Q.......X...... ......nnnnnddddd Sd Vn (fmaxnmv, fmaxv, fminnmv, fminv)
case IF_DV_2S: // DV_2S ........XX...... ......nnnnnddddd Sd Vn (addp - scalar)
elemsize = id->idOpSize();
case IF_DV_2T: // DV_2T .Q......XX...... ......nnnnnddddd Sd Vn (addv, saddlv, smaxv, sminv, uaddlv,
// umaxv, uminv)
elemsize = optGetElemsize(id->idInsOpt());
emitDispReg(id->idReg1(), elemsize, true);
emitDispVectorReg(id->idReg2(), id->idInsOpt(), false);
break;
Expand Down
1 change: 1 addition & 0 deletions src/coreclr/src/jit/emitfmtsarm64.h
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Original file line number Diff line number Diff line change
Expand Up @@ -199,6 +199,7 @@ IF_DEF(DV_2P, IS_NONE, NONE) // DV_2P ................ ......nnnnnddddd V
IF_DEF(DV_2Q, IS_NONE, NONE) // DV_2Q .........X...... ......nnnnnddddd Sd Vn (faddp, fmaxnmp, fmaxp, fminnmp, fminp - scalar)
IF_DEF(DV_2R, IS_NONE, NONE) // DV_2R .Q.......X...... ......nnnnnddddd Sd Vn (fmaxnmv, fmaxv, fminnmv, fminv)
IF_DEF(DV_2S, IS_NONE, NONE) // DV_2S ........XX...... ......nnnnnddddd Sd Vn (addp - scalar)
IF_DEF(DV_2T, IS_NONE, NONE) // DV_2T .Q......XX...... ......nnnnnddddd Sd Vn (addv, saddlv, smaxv, sminv, uaddlv, umaxv, uminv)

IF_DEF(DV_3A, IS_NONE, NONE) // DV_3A .Q......XX.mmmmm ......nnnnnddddd Vd Vn Vm (vector)
IF_DEF(DV_3AI, IS_NONE, NONE) // DV_3AI .Q......XXLMmmmm ....H.nnnnnddddd Vd Vn Vm[] (vector by elem)
Expand Down
14 changes: 7 additions & 7 deletions src/coreclr/src/jit/hwintrinsic.cpp
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Expand Up @@ -247,20 +247,20 @@ unsigned HWIntrinsicInfo::lookupSimdSize(Compiler* comp, NamedIntrinsic id, CORI

CORINFO_CLASS_HANDLE typeHnd = nullptr;

if (JITtype2varType(sig->retType) == TYP_STRUCT)
{
typeHnd = sig->retTypeSigClass;
}
else if (HWIntrinsicInfo::BaseTypeFromFirstArg(id))
if (HWIntrinsicInfo::BaseTypeFromFirstArg(id))
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{
typeHnd = comp->info.compCompHnd->getArgClass(sig, sig->args);
}
else
else if (HWIntrinsicInfo::BaseTypeFromSecondArg(id))
{
assert(HWIntrinsicInfo::BaseTypeFromSecondArg(id));
CORINFO_ARG_LIST_HANDLE secondArg = comp->info.compCompHnd->getArgNext(sig->args);
typeHnd = comp->info.compCompHnd->getArgClass(sig, secondArg);
}
else
{
assert(JITtype2varType(sig->retType) == TYP_STRUCT);
typeHnd = sig->retTypeSigClass;
}

unsigned simdSize = 0;
var_types baseType = comp->getBaseTypeAndSizeOfSIMDType(typeHnd, &simdSize);
Expand Down
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