v1.3.0

Feature

(#261) Bump sbt to 1.3.2

v1.3.0-RC2

Feature

(#259) Bump sbt to 1.3.0

v1.3.0-RC1

Fix

(#208) Cleanup harness generation and add missing vl_finish().

(#227) Treadle was not working with composite memories

(#238) Fix RerunWithoutElaboration

(#239) Fix problem with circuits with zero width input using verilator

Feature

(#196) Adapt to Cleaning up BlackBoxSourceHelper

(#197) Cleanup deprecated loadAnnotations call.

(#199) Add iverilog as a backend

(#200) More BlackBoxSourceHelper cleanup adaptation

(#201) Enable VCS blackbox test.

(#202) Add mill support.

(#203) Bump downloaded mill version.

(#204) Bump to Scala 2.12.6 and make it the default.

(#205) Add treadle support.

(#206) Test memory loading

(#211) Add flag to stop verilator simulation from writing a VCD

(#212) Bump scopt version to match other projects.

(#214) Add support for vcs command line options to verilator.

(#217) Fix typo in editableBuildCommandTests

(#219) Bump sbt to 1.2.6; update dependencies

(#221) Add enum support

(#222) Bump SBT from 1.2.6 to 1.2.7 to fix partial recompilation issue

(#232) Bump copyright year

(#235) Update publishVersion in build.sc to match build.sbt

(#240) Filter TargetDirAnnotations between Driver.execute

(#241) Centralize (for testers) annotation filtering and filter out some more -

(#248) Removed redundant text in doc

(#249) Quick fix (hack) for Stage/Phase CircuitForm issues.

(#252) Change the verilator generation code to call dut->eval() instead

(#254) Bump dependency versions

(#255) Support migration of dontTouch, RawModule, MultiIOModule from experimental

v1.2.10

Bump for chisel v3.1.8

v1.2.9

The release incorporates the following fixes:

• bump FIRRTL dependency to 1.1.7

v1.2.8

Bump FIRRTL version.

v1.2.7

Bump FIRRTL version to 1.1.5

v1.2.6

This release bumps the firrtl and chisel dependencies to 1.1.4 and 3.1.4 respectively and adds the following features and bug fixes:

• Fix typo in editableBuildCommandTests (#217)
• Add support for vcs command line options to verilator. (#214)
• Bump scopt version to match other projects. (#212)
• Test memory loading (#206)
• Enable VCS blackbox test. (#201)
• Convert to BlackBoxSourceHelper.fileListName (lower case 'f') (#196, #200)

v1.2.5

Add support to enable/disable VCD file generation regardless of backend implementation defaults.

• added --generate-vcd-output flag with possible values off or on.

v1.2.4

This release updates the Chisel dependencies:

• chisel3 -> 3.1.3
• firrtl -> 1.1.3
• firrtl-interpreter -> 1.1.3
• treadle -> 1.0.1