[ExportVerilog] Fix ifdef of macro w/ Verilog name #6956
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| name: Windows build and test | |
| # Run on main (after PRs land) to ensure that they aren't heinously breaking the | |
| # Windows build. | |
| on: | |
| push: | |
| branches: | |
| - main | |
| workflow_dispatch: | |
| jobs: | |
| # Build CIRCT and run its tests. | |
| build-circt: | |
| name: Build and Test | |
| uses: ./.github/workflows/unifiedBuildTestAndInstall.yml | |
| # This should not be needed, but the unified job unconditionally requires this permission currently. | |
| permissions: | |
| contents: write # Upload assets to release. | |
| with: | |
| runner: windows-2022 | |
| cmake_build_type: release | |
| llvm_enable_assertions: ON | |
| build_shared_libs: OFF | |
| llvm_force_enable_stats: ON | |
| runTests: true | |
| cmake_c_compiler: cl | |
| cmake_cxx_compiler: cl |