[ExportVerilog] Fix ifdef of macro w/ Verilog name #7947
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uenoku
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Dec 4, 2024
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darthscsi
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Dec 4, 2024
Add a utility function to `sv.macro.decl` that can be used to get its Verilog textual macro identifier name. This is added for convenience to avoid having to repeat the patter of getting its optional Verilog name or symbol name. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Fix a bug in the emission of `sv.ifdef` (and its procedural variant) where the symbol name was always used instead of using the symbol name only if a Verilog name was not specified. This is done to fix an issue related to lowering of FIRRTL inline layers where the `LowerLayers` pass generates new `sv.macro.decl` symbols that will replace existing `firrtl.layer` symbols. However, it relies on a namespace to generate these and will result in suffixed symbol names. (It could obviously do more work to conserve symbols or generate in-pass invalid IR with duplicate symbols.) Nonetheless, the real bug here is that the `ExportVerilog` conversion is not doing the right thing with the Verilog name attribute. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
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Add a utility function to
sv.macro.declthat can be used to get itsVerilog textual macro identifier name. This is added for convenience to
avoid having to repeat the patter of getting its optional Verilog name or
symbol name.
This is done to fix an issue related to lowering of FIRRTL inline layers
where the
LowerLayerspass generates newsv.macro.declsymbols thatwill replace existing
firrtl.layersymbols. However, it relies on anamespace to generate these and will result in suffixed symbol names. (It
could obviously do more work to conserve symbols or generate in-pass
invalid IR with duplicate symbols.) Nonetheless, the real bug here is
that the
ExportVerilogconversion is not doing the right thing with theVerilog name attribute.