[lib] update vtr to latest

[tangxifan]

Motivate of the pull request

• To address an existing issue. If so, please provide a link to the issue: Bump vtr-verilog-to-routing from 04959b7 to 8178b71 #1895
• Breaking new feature. If so, please describe details in the description part.

Describe the technical details

What is currently done? (Provide issue link if applicable)

Currently, OpenFPGA has the following limitations:

• As seen in Bump vtr-verilog-to-routing from 04959b7 to 8178b71 #1895, due to VPR API grades, OpenFPGA codes require an update to be compatible

What does this pull request change?

This PR improves in the following aspects:

• Adapt to latest VPR's API on direct connections

Which part of the code base require a change

• VPR
• Tileable routing architecture generator
• OpenFPGA libraries
• FPGA-Verilog
• FPGA-Bitstream
• FPGA-SDC
• FPGA-SPICE
• Flow scripts
• Architecture library
• Cell library
• Documentation
• Regression tests
• Continous Integration (CI) scripts

Impact of the pull request

• Require a change on Quality of Results (QoR)
• Break back-compatibility. If so, please list who may be influenced.