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Architecture and regression test update #90
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tangxifan
commented
Sep 22, 2020
- Added k4_n4 series architectures covering memory, hard adder and fracturable 32-bit multiplier
- Added test cases for the new architectures
- Added Verilog netlists for the primitive blocks in the new architectures
- Added test cases for using multiple routing segments in FPGA
- Bug fix for tileable routing resource graph generator when multiple routing segments are used
LNIS-Projects
approved these changes
Sep 22, 2020
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