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Update esl_epfl_x_heep to esl-epfl/x-heep@76d58ef
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Update code from upstream repository https://github.com/esl-
epfl/x-heep.git to revision 76d58efe7b9dec0723c1cb9aaf8ad76ad6c85373

* Update ci (esl-epfl/x-heep#454) (Luigi Giuffrida)
* fix num of FPGAs in README (Davide Schiavone)
* Porting Ultrascale ZCU104 board (esl-epfl/x-heep#435) (jmiranda)
* Add absolute path to `CMakeLists.txt` match statements (esl-
  epfl/x-heep#469) (Michele Caon)
* add SystemC example (esl-epfl/x-heep#443) (Davide Schiavone)
* Structs multireg fix (esl-epfl/x-heep#466) (Stefano Albini)
* add Coremark and update cv32e40p (esl-epfl/x-heep#465) (Davide
  Schiavone)
* add tiled matmul (esl-epfl/x-heep#464) (Davide Schiavone)
* fix software errors/warnings (esl-epfl/x-heep#462) (Davide
  Schiavone)
* add xcelium support (esl-epfl/x-heep#452) (Davide Schiavone)
* Add matmul example (esl-epfl/x-heep#461) (Davide Schiavone)
* fix typo in debug_ss (esl-epfl/x-heep#460) (Luigi Giuffrida)
* update riscv_dbg (esl-epfl/x-heep#230) (Davide Schiavone)
* Fix esl-epfl/x-heep#430 (esl-epfl/x-heep#459) (David Mallasén
  Quintana)
* fix esl-epfl/x-heep#447 (esl-epfl/x-heep#453) (Davide Schiavone)
* fix typo (esl-epfl/x-heep#458) (Luigi Giuffrida)
* add OpenOCD BSCAN configuration file  (esl-epfl/x-heep#457) (Luis
  Waucquez)
* Removed repeated code in dma hal (esl-epfl/x-heep#456) (Juan-n-only)
* Fix linker script generation (esl-epfl/x-heep#451) (Luigi Giuffrida)
* Add a target to the Makefile to directly program the FPGA (esl-
  epfl/x-heep#450) (Luigi Giuffrida)
* [hw/sw] update flash load linker script, data_interleaved and
  data_flash_only sections (esl-epfl/x-heep#399) (Davide Schiavone)
* add simple accelerator example (esl-epfl/x-heep#446) (Davide
  Schiavone)
* change python format for Bootrom (esl-epfl/x-heep#442) (Davide
  Schiavone)
* fix memset bug (esl-epfl/x-heep#439) (Mattia Consani)
* update cv32e40px with dual-read support (esl-epfl/x-heep#441)
  (Davide Schiavone)
* Added X-HEEP Reference. (esl-epfl/x-heep#440) (Simone Machetti)
* add w25q128 flash BSP (esl-epfl/x-heep#433) (Mattia Consani)
* removed FEMU (esl-epfl/x-heep#437) (Simone Machetti)
* update cve2 (esl-epfl/x-heep#284) (Davide Schiavone)
* porting X-HEEP to the nexys FPGA (esl-epfl/x-heep#432) (Davide
  Schiavone)
* Add standard and quad write functionality to flash model (esl-
  epfl/x-heep#426) (Mattia Consani)
* revert 🐛 introduced in last revendor of iceprog (davide
  schiavone)
* Add `example_spi_host_quadIO`  (esl-epfl/x-heep#401) (Mattia
  Consani)
* fix minimal cfg with stack and heap size (esl-epfl/x-heep#431)
  (Davide Schiavone)
* Update verible url (esl-epfl/x-heep#428) (David Mallasén Quintana)
* expose DMA slots externally + external FIFO example (esl-
  epfl/x-heep#417) (grinningmosfet)
* Updated the documentation on how to add external interrupts (esl-
  epfl/x-heep#427) (Juan-n-only)
* add citation in readme (Davide Schiavone)
* Fix run-blinky-freertos command (esl-epfl/x-heep#424) (jmiranda)
* Compilation fix (esl-epfl/x-heep#422) (jmiranda)
* add stack and heap size as parameters to mcu-gen (esl-
  epfl/x-heep#419) (Luigi Giuffrida)

Signed-off-by: mbelda <11842513+mbelda@users.noreply.github.com>
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mbelda committed Mar 15, 2024
1 parent 59cebb8 commit cf060eb
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6 changes: 1 addition & 5 deletions hw/vendor/esl_epfl_x_heep/.gitignore
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Original file line number Diff line number Diff line change
Expand Up @@ -7,16 +7,12 @@ build/
*.dis
*.map
*.do
.venv/*
.venv/
util/__pycache__/*

# ignore apps output file
run_verif_rtl_log.txt

#ignore femu generated hw
linux_femu/rtl/linux_femu.sv
.venv/

# ignore the following hw automatically generated files
environment.yml
core-v-mini-mcu.upf
Expand Down
71 changes: 55 additions & 16 deletions hw/vendor/esl_epfl_x_heep/Makefile
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Original file line number Diff line number Diff line change
Expand Up @@ -6,6 +6,7 @@ MAKE = make

# Get the absolute path
mkfile_path := $(shell dirname "$(realpath $(firstword $(MAKEFILE_LIST)))")
$(info $$You are executing from: $(mkfile_path))

# Include the self-documenting tool
FILE=$(mkfile_path)/Makefile
Expand Down Expand Up @@ -33,7 +34,7 @@ PROJECT ?= hello_world
# Linker options are 'on_chip' (default),'flash_load','flash_exec','freertos'
LINKER ?= on_chip

# Target options are 'sim' (default) and 'pynq-z2'
# Target options are 'sim' (default) and 'pynq-z2' and 'nexys-a7-100t'
TARGET ?= sim
MCU_CFG ?= mcu_cfg.hjson
PAD_CFG ?= pad_cfg.hjson
Expand All @@ -49,28 +50,46 @@ COMPILER_PREFIX ?= riscv32-unknown-
ARCH ?= rv32imc

# Path relative from the location of sw/Makefile from which to fetch source files. The directory of that file is the default value.
SOURCE ?= "."
SOURCE ?= $(".")

# Simulation engines options are verilator (default) and questasim
SIMULATOR ?= verilator

# Timeout for simulation, default 120
TIMEOUT ?= 120

# Flash read address for testing, in hexadecimal format 0x0000
FLASHREAD_ADDR ?= 0x0
FLASHREAD_FILE ?= $(mkfile_path)/flashcontent.hex
FLASHREAD_BYTES ?= 256

#max address in the hex file, used to program the flash
ifeq ($(wildcard sw/build/main.hex),)
MAX_HEX_ADDRESS = 0
MAX_HEX_ADDRESS_DEC = 0
BYTES_AFTER_MAX_HEX_ADDRESS = 0
FLASHRWITE_BYTES = 0
else
MAX_HEX_ADDRESS = $(shell cat sw/build/main.hex | grep "@" | tail -1 | cut -c2-)
MAX_HEX_ADDRESS_DEC = $(shell printf "%d" 0x$(MAX_HEX_ADDRESS))
BYTES_AFTER_MAX_HEX_ADDRESS = $(shell tac sw/build/main.hex | awk 'BEGIN {count=0} /@/ {print count; exit} {count++}')
FLASHRWITE_BYTES = $(shell echo $(MAX_HEX_ADDRESS_DEC) + $(BYTES_AFTER_MAX_HEX_ADDRESS)*16 | bc)
endif


#binary to store in flash memory
FLASHWRITE_FILE = $(mkfile_path)/sw/build/main.hex

# Export variables to sub-makefiles
export

## @section Conda
conda: environment.yml
conda env create -f environment.yml

environment.yml: python-requirements.txt
util/python-requirements2conda.sh

## @section Linux-Emulation

## Generates FEMU
linux-femu-gen: mcu-gen
$(PYTHON) util/mcu_gen.py --cfg $(MCU_CFG) --pads_cfg $(PAD_CFG) --outdir linux_femu/rtl/ --tpl-sv linux_femu/rtl/linux_femu.sv.tpl
$(MAKE) verible

## @section Installation

## Generates mcu files core-v-mini-mcu files and build the design with fusesoc
Expand Down Expand Up @@ -115,7 +134,7 @@ verible:

## Generates the build folder in sw using CMake to build (compile and linking)
## @param PROJECT=<folder_name_of_the_project_to_be_built>
## @param TARGET=sim(default),pynq-z2
## @param TARGET=sim(default),systemc,pynq-z2,nexys-a7-100t,zcu104
## @param LINKER=on_chip(default),flash_load,flash_exec
## @param COMPILER=gcc(default), clang
## @param COMPILER_PREFIX=riscv32-unknown-(default)
Expand All @@ -134,10 +153,14 @@ app-compile-all:

## @section Simulation

## Verilator simulation
## Verilator simulation with C++
verilator-sim:
$(FUSESOC) --cores-root . run --no-export --target=sim --tool=verilator $(FUSESOC_FLAGS) --build openhwgroup.org:systems:core-v-mini-mcu ${FUSESOC_PARAM} 2>&1 | tee buildsim.log

## Verilator simulation with SystemC
verilator-sim-sc:
$(FUSESOC) --cores-root . run --no-export --target=sim_sc --tool=verilator $(FUSESOC_FLAGS) --build openhwgroup.org:systems:core-v-mini-mcu ${FUSESOC_PARAM} 2>&1 | tee buildsim.log

## Questasim simulation
questasim-sim:
$(FUSESOC) --cores-root . run --no-export --target=sim --tool=modelsim $(FUSESOC_FLAGS) --build openhwgroup.org:systems:core-v-mini-mcu ${FUSESOC_PARAM} 2>&1 | tee buildsim.log
Expand All @@ -161,6 +184,10 @@ vcs-sim:
vcs-ams-sim:
$(FUSESOC) --cores-root . run --no-export --target=sim --flag "ams_sim" --tool=vcs $(FUSESOC_FLAGS) --build openhwgroup.org:systems:core-v-mini-mcu ${FUSESOC_PARAM} 2>&1 | tee buildsim.log

## xcelium simulation
xcelium-sim:
$(FUSESOC) --cores-root . run --no-export --target=sim --tool=xcelium $(FUSESOC_FLAGS) --build openhwgroup.org:systems:core-v-mini-mcu ${FUSESOC_PARAM} 2>&1 | tee buildsim.log

## Generates the build output for helloworld application
## Uses verilator to simulate the HW model and run the FW
## UART Dumping in uart0.log to show recollected results
Expand All @@ -175,7 +202,7 @@ run-helloworld: mcu-gen verilator-sim
## Uses verilator to simulate the HW model and run the FW
## UART Dumping in uart0.log to show recollected results
run-blinkyfreertos: mcu-gen verilator-sim
$(MAKE) -C sw PROJECT=blinky_freertos TARGET=$(TARGET) LINKER=$(LINKER) COMPILER=$(COMPILER) COMPILER_PREFIX=$(COMPILER_PREFIX) ARCH=$(ARCH);
$(MAKE) -C sw PROJECT=example_freertos_blinky TARGET=$(TARGET) LINKER=$(LINKER) COMPILER=$(COMPILER) COMPILER_PREFIX=$(COMPILER_PREFIX) ARCH=$(ARCH);
cd ./build/openhwgroup.org_systems_core-v-mini-mcu_0/sim-verilator; \
./Vtestharness +firmware=../../../sw/build/main.hex; \
cat uart0.log; \
Expand All @@ -196,14 +223,17 @@ app-simulate-all:
## @section Vivado

## Builds (synthesis and implementation) the bitstream for the FPGA version using Vivado
## @param FPGA_BOARD=nexys-a7-100t,pynq-z2
## @param FPGA_BOARD=nexys-a7-100t,pynq-z2,zcu104
## @param FUSESOC_FLAGS=--flag=<flagname>
vivado-fpga:
$(FUSESOC) --cores-root . run --no-export --target=$(FPGA_BOARD) $(FUSESOC_FLAGS) --build openhwgroup.org:systems:core-v-mini-mcu ${FUSESOC_PARAM} 2>&1 | tee buildvivado.log

vivado-fpga-nobuild:
$(FUSESOC) --cores-root . run --no-export --target=$(FPGA_BOARD) $(FUSESOC_FLAGS) --setup openhwgroup.org:systems:core-v-mini-mcu ${FUSESOC_PARAM} 2>&1 | tee buildvivado.log

vivado-fpga-pgm:
$(MAKE) -C build/openhwgroup.org_systems_core-v-mini-mcu_0/$(FPGA_BOARD)-vivado pgm

## @section ASIC
## Note that for this step you need to provide technology-dependent files (e.g., libs, constraints)
asic:
Expand All @@ -220,18 +250,27 @@ openroad-sky130:

## Read the id from the EPFL_Programmer flash
flash-readid:
cd sw/vendor/yosyshq_icestorm/iceprog; \
cd sw/vendor/yosyshq_icestorm/iceprog; make; \
./iceprog -d i:0x0403:0x6011 -I B -t;

## Loads the obtained binary to the EPFL_Programmer flash
flash-prog:
cd sw/vendor/yosyshq_icestorm/iceprog; \
./iceprog -d i:0x0403:0x6011 -I B $(mkfile_path)/sw/build/main.hex;
cd sw/vendor/yosyshq_icestorm/iceprog; make; \
./iceprog -a $(FLASHRWITE_BYTES) -d i:0x0403:0x6011 -I B $(FLASHWRITE_FILE);

## Read the EPFL_Programmer flash
flash-read:
cd sw/vendor/yosyshq_icestorm/iceprog; make; \
./iceprog -d i:0x0403:0x6011 -I B -o $(shell printf "%d" $(FLASHREAD_ADDR)) -R $(FLASHREAD_BYTES) $(FLASHREAD_FILE);

## Run openOCD w/ EPFL_Programmer
openOCD_epflp:
xterm -e openocd -f ./tb/core-v-mini-mcu-pynq-z2-esl-programmer.cfg;

## Run openOCD w/ BSCAN of the Pynq-Z2 board
openOCD_bscan:
xterm -e openocd -f ./tb/core-v-mini-mcu-pynq-z2-bscan.cfg;

## Start GDB
gdb_connect:
$(MAKE) -C sw gdb_connect
Expand Down
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