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Here are 88 public repositories matching this topic...

pConst / basic_verilog

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Must-have verilog systemverilog modules

Updated Nov 7, 2024
Verilog

ultraembedded / biriscv

Sponsor

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32-bit Superscalar RISC-V CPU

linux asic cpu fpga verilog xilinx superscalar in-order risc-v branch-prediction coremark rv32i verilator riscv-linux rv32im artix-7 pipelined-processors

Updated Sep 18, 2021
Verilog

open-sdr / openwifi-hw

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open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware

linux fpga zynq hls hardware vhdl rtl verilog xilinx sdr wi-fi analog-devices ieee80211 dma software-defined-radio ofdm csma ad9361 mac80211

Updated Dec 1, 2024
Verilog

ZipCPU / wb2axip

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Bus bridges and other odds and ends

fpga gplv3 xilinx wishbone xilinx-vivado wishbone-bus axi-bus

Updated Jan 1, 2025
Verilog

lastweek / fpga_readings

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Recipe for FPGA cooking

fpga hls rtl verilog xilinx vivado-hls

Updated Sep 29, 2024
Verilog

nxbyte / Verilog-Projects

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This repository contains source code for past labs and projects involving FPGA and Verilog based designs

simulator encoder decoder priority verilog xilinx testbenches multiplexer comparator adder system-verilog xilinx-vivado half-adder traffic-light-controller full-adder ripple-adder look-ahead-adder

Updated Oct 2, 2019
Verilog

nxbyte / ARM-LEGv8

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Verilog Implementation of an ARM LEGv8 CPU

arm verilog xilinx isa vivado hazard-detection ldr pipeline-cpu single-cycle hennessy patterson legv8-arm multi-cycle arm-legv8-simulator forwarding-unit

Updated Oct 3, 2018
Verilog

chipsalliance / yosys-f4pga-plugins

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Plugins for Yosys developed as part of the F4PGA project.

toolchain fpga eda xilinx yosys xilinx-fpga yosys-plugin f4pga

Updated May 14, 2024
Verilog

OVGN / OpenHBMC

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Open-source high performance AXI4-based HyperRAM memory controller

fpga xilinx vivado

Updated Oct 6, 2022
Verilog

Parretto / DisplayPort

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DisplayPort IP-core

fpga xilinx lattice ip-core displayport

Updated Oct 25, 2024
Verilog

pontazaricardo / Verilog_Calculator_Matrix_Multiplication

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This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.

calculator vhdl matrix-multiplication verilog xilinx hardware-designs xilinx-fpga low-level-programming xilinx-ise xilinx-vivado ic-design

Updated Aug 12, 2017
Verilog

jfoshea / Viterbi-Decoder-in-Verilog

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An efficient implementation of the Viterbi decoding algorithm in Verilog

viterbi-algorithm fpga xilinx verilog-hdl viterbi-decoder

Updated Mar 15, 2024
Verilog

Elphel / eddr3

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mirror of https://git.elphel.com/Elphel/eddr3

fpga zynq ddr verilog xilinx open-core ddr3 memory-controller

Updated Oct 16, 2017
Verilog

tongplw / HW-Syn-Lab

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⚙Hardware Synthesis Laboratory Using Verilog

hardware verilog xilinx vivado uart vga basys3 hardware-synthesis

Updated May 10, 2020
Verilog

Elphel / x393

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mirror of https://git.elphel.com/Elphel/x393

fpga camera verilog xilinx machine-vision imaging open-core nc393

Updated Mar 16, 2023
Verilog

ahirsharan / 32-Bit-Floating-Point-Adder

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Verilog Implementation of 32-bit Floating Point Adder

verilog xilinx vlsi

Updated May 4, 2020
Verilog

Xilinx / xup_fpga_vivado_flow

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AMD Xilinx University Program Vivado tutorial

fpga hardware xilinx vivado

Updated Feb 13, 2023
Verilog

JeffDeCola / my-verilog-examples

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A place to keep my synthesizable verilog examples.

simulator asic fpga hardware waveform verilog xilinx synthesis vivado systemverilog gtkwave hdl iverilog hardware-description-language verilog-simulator asic-design synthesize hardware-architecture

Updated Jul 10, 2023
Verilog

Goshik92 / SHA256Hasher

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SHA-256 IP core for ZedBoard (Zynq SoC)

arm fpga zynq xilinx sha256 vivado systemverilog soc zedboard

Updated Jun 22, 2018
Verilog

leonow32 / verilog-fpga

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Many peripherals in Verilog ready to use

fpga verilog xilinx altera systemverilog lattice cpld machxo2 machxo

Updated Dec 29, 2024
Verilog

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xilinx

Here are 88 public repositories matching this topic...

pConst / basic_verilog

ultraembedded / biriscv

open-sdr / openwifi-hw

ZipCPU / wb2axip

lastweek / fpga_readings

nxbyte / Verilog-Projects

nxbyte / ARM-LEGv8

chipsalliance / yosys-f4pga-plugins

OVGN / OpenHBMC

Parretto / DisplayPort

pontazaricardo / Verilog_Calculator_Matrix_Multiplication

jfoshea / Viterbi-Decoder-in-Verilog

Elphel / eddr3

tongplw / HW-Syn-Lab

Elphel / x393

ahirsharan / 32-Bit-Floating-Point-Adder

Xilinx / xup_fpga_vivado_flow

JeffDeCola / my-verilog-examples

Goshik92 / SHA256Hasher

leonow32 / verilog-fpga

Improve this page

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