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@ycsin ycsin commented Aug 14, 2024

Backport the end result of #76045, #76791 & #77047

Fixes #76762

ycsin added 2 commits August 14, 2024 15:18
Account for the scenario when we are doing `esf`-based
unwinding from a function which doesn't have any callee.
In this case the `ra` is not saved on the stack and the
second function from the top of the frame could be missing.

Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
qemu_riscv32e uses a different ISA and is kinda special, add it
to the testcase for better coverage.

Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
@ycsin ycsin added this to the v3.7.1 milestone Aug 14, 2024
@ycsin ycsin marked this pull request as ready for review September 3, 2024 06:03
@zephyrbot zephyrbot added area: Architectures area: RISCV RISCV Architecture (32-bit & 64-bit) labels Sep 3, 2024
@ycsin ycsin changed the title [Backport v3.7-branch] arch: riscv: stacktrace: fix output without ra on the stack top [Backport v3.7-branch] arch: riscv: stacktrace: fix output without ra on the stack top Sep 3, 2024
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LGTM

@nashif nashif merged commit 34a68c4 into zephyrproject-rtos:v3.7-branch Oct 15, 2024
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@ycsin ycsin deleted the pr/v3.7-backport-trace-fixes branch October 16, 2024 11:02
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v3.7-branch: arch: riscv: stacktrace: trace is incomplete when unwinding from function without callee
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