Inst_Old

Instructions

This is a list of the available registers, OpCodes / Instructions, and what they mean. These were all reverse engineered by just looking at existing code and recognizing patterns. As such, this list may be incomplete or full of errors. Any resemblance to the mnemonics or syntax used by other processors, such as the 8086, is simply because we borrowed existing syntax where it seemed fit. The CPU5 and CPU6 are both evolutions of the older CPU4 design, which itself was either heavily inspired by or a direct copy of the Eldorado Electrodata Corporation EE200. Documentation on the EE200 can be found here.

Registers

There are eight registers available, though care should be taken with some registers, particularly the X, S, C and P registers, as these are used for specific functions during some OpCodes.

Each register is addressed by its nibble. For word operations, use the Leftmost nibble. For byte operations, the nibble corresponds to the high byte or low byte.

Ex.:

AW = 0, AH = 0, AL = 1

BW = 2, BH = 2, BL = 3

Name	Byte	Full Word	High Byte	Low Byte	Usage	Notes
A	01	AW	AH	AL	Primary Accumulator	Primary register, commonly used in implicit operations, can use full addressing modes
B	23	BW	BH	BL	Secondary Accumulator	Primary register, commonly used in implicit operations, can use full addressing modes
X	45	XW			Primary Index	Can only do word operations (Not true for CPU6?)
Y	67	YW	YH	YL	Secondary Index or Working Register	Index registers or working storage registers
Z	89	ZW	ZH	ZL	Secondary Index or Working Register	Index registers or working storage registers
S	AB	SW	SH	SL	Stack Register	Global among all interrupt levels and used to maintain stack during subroutine exits and entries
C	CD				Context Register	Contains the status condition indicators (fault, link, minus, and value) and preceding interrupt level
P	EF				Program Counter Base	Contains initial program counter value to be used when starting up or returning from interrupt

Contexts

Each register and the flags appears to exist in 16 contexts and these contexts are mapped between 0x0000 and 0x00FF 16 bytes per context starting with context 0 and working upwards. The registers are stored in the memory in the order given above. Writing to the memory of another context updates the registers for that context. Writing to the memory for your own context appears to change the register value except for P and C.

The processor starts in context 0. Context 15 is used by what appears to be a syscall instruction, context 6 is used by the MUX interrupt test, context 1 is used programmatically during MMU testing.

Interrupts (or at least the one sample we have) are processed by a hardware triggered context switch, the execution of code in the new context, and then an 0x0A instruction.

Context Register

The context register holds the previous IPL, the condition codes and the Page Table Map register.

The register organisation is as follows

Bit(s)	Function
15-12	Previous IPL
11-8	Unknown, not used?
7	Value (Zero)
6	Minus (Sign)
5	Fault (Overflow)
4	Link (Carry)
3-0	Page Table Map for context

Instruction Organization

Instructions are constructed a nibble at a time, like a Build a Bear. The high nibble of the high byte determines what kind of operation is being executed. It should be noted that the lowest bit of the high nibble determines whether we are doing a byte operation or a word operation (excluding Control, Branch, X register and Jump operations). For example, 0x8 is 1000 in binary and is a byte operation. 0x9 is 1001 in binary and is a word operation. Both operation load the A register, but the low bit being either "0" or "1" is what determines whether we are loading a byte or word.

High nibble	Operation type
0x0	Control instructions
0x1	Conditional branch instructions
0x2	Single Register byte operations
0x3	Single register word operations
0x4	Double register byte operations
0x5	Double register word operations
0x6	X register memory reference operations
0x7	Jump operations
0x8	A register load byte operations
0x9	A register load word operations
0xA	A register store byte operations
0xB	A register store word operations
0xC	B register load byte operations
0xD	B register load word operations
0xE	B register store byte operations
0xF	B register store word operations

Addressing Modes

Instructions can be either 1-byte, 2-byte or 3-byte depending on the type of instruction. The second or third byte (if present) are related to addressing, or directing the instruction as to which location in memory to act upon. Addressing can be either implicit or explicit. Implicit means that no addressing is specified, and that specific instruction operates on only one specific location. Explicit means the programmer must state which location they will perform the operation on.

In the chart below, the addressing mode and what is expected at each nibble of each operation is shown.

HB = High Byte; MB = Mid Byte; LB = Low Byte

HN = High Nibble; LN = Low Nibble

HB_HN	HB_LN	MB_HN	MB_LN	LB_HN	LB_LN	Note
0	Op (0-F)					Control Operations

1	Op (0-F)	Displace	Displace			Branch Operations

2	Op (0-7)	Source Reg.	Constant			Single Register Explicit Byte Operation
2	Op (8-F)					Single Register Implicit Byte Operation
3	Op (0-7)	Source Reg.	Constant			Single Register Explicit Word Operation
3	Op (8-F)					Single Register Implicit Word Operation

4	Op (0-7)	Source Reg.	Dest. Reg.			Double Register Explicit Byte Operation
4	Op (8-F)					Double Register Implicit Byte Operation
5	Op (0-7)	Source Reg.	Dest. Reg.			Double Register Explicit Word Operation
5	Op (8-F)					Double Register Implicit Word Operation

Op (6-F)	0	Literal	Literal			Literal Memory Address Byte Operation
Op (6-F)	0	Literal	Literal	Literal	Literal	Literal Memory Address Word Operation
Op (6-F)	1	Direct	Direct	Direct	Direct	Direct Memory Address Operation
Op (6-F)	2	Indirect	Indirect	Indirect	Indirect	Indirect Memory Address Operation
Op (6-F)	3	Displace	Displace			Relative to Current Location Memory Address Operation
Op (6-F)	4	Displace	Displace			Indirect Relative to Current Location Memory Address Operation
Op (6-F)	5	Register	Modifier	Displace	Displace	Indexed Addressing (Modifier Table Below)
Op (6-F)	8-F					Implicit Indexing (8 - F => A - P Reg.)

Modifier	Note
0	Use register as address (2-byte)
1	Use register as address and increment after (2-byte)
2	Decrement register and then use as address (2-byte)

4	Use register as indirect address (2-byte)
5	Use register as indirect address and increment after (2-byte)
6	Decrement register and then use as indirect address (2-byte)

8	Add displacement byte to register and use as address (3-byte)
9	Add displacement byte to register and use as address, then increment (3-byte)
A	Decrement register, add displacement byte to register and use as address (3-byte)

C	Add displacement byte to register and use as indirect address (3-byte)
D	Add displacement byte to register and use as indirect address, then increment (3-byte)
E	Decrement register, add displacement byte to register and use as indirect address (3-byte)

Full Instruction List

This is a full list of instructions in order of hexadecimal value. Depending on the operation, this may not be the most effective way of looking up an instruction but is included for completeness.

Note: Despite saying "completeness" in the previous sentence, this list is very much so incomplete and a constant work in progress. If something seems incredibly strange or broken, it most likely is.

Hex	Binary	OpCode Byte	Address Byte	Address Byte	Notes
00	0000 0000	HLT			Halts the CPU
01	0000 0001	NOP			No Operation
02	0000 0010	SF			Set Fault
03	0000 0011	RF			Reset Fault
04	0000 0100	EI			Enable the Interrupt System
05	0000 0101	DI			Disable the Interrupt System
06	0000 0110	SL			Set the Link/carry Flag
07	0000 0111	RL			Reset the Link/carry Flag
08	0000 1000	CL			Complement Link
09	0000 1001	RSR			Return from subroutine
0A	0000 1010	RI			Return from interrupt
0B	0000 1011	RIM			Return from Interrupt Modified. Possibly illegal instruction on the CPU6
0C	0000 1100	ELO			Enable Link Out on EE200. CPU6 will flash the ABT light on the front panel
0D	0000 1101	PCX			Transfer PC to X
0E	0000 1110	DLY			Delay 4.5 ms
0F	0000 1111	RSYS			Return from JSYS using stack. (pops a byte, PC <- X, then pops the new value of X, then the new IPL, then the new Page Table Map). See also JSYS

10	0001 0000	BL	PC+N		Branch if Link/Carry Set
11	0001 0001	BNL	PC+N		Branch if Link/Carry not Set
12	0001 0010	BF	PC+N		Branch if Fault Set
13	0001 0011	BNF	PC+N		Branch if Fault not Set
14	0001 0100	BZ	PC+N		Branch if Equal to 0
15	0001 0101	BNZ	PC+N		Branch if Not Equal to 0
16	0001 0110	BM	PC+N		Branch if Minus set
17	0001 0111	BP	PC+N		Branch on Positive
18	0001 1000	BGZ	PC+N		Branch if Greater Than 0
19	0001 1001	BLE	PC+N		Branch if Less Than or Equal to 0
1A	0001 1010	BS1	PC+N		Branch if Sense Switch 1 Set
1B	0001 1011	BS2	PC+N		Branch if Sense Switch 2 Set
1C	0001 1100	BS3	PC+N		Branch if Sense Switch 3 Set
1D	0001 1101	BS4	PC+N		Branch if Sense Switch 4 Set
1E	0001 1110	BIE			Branch on interrupts enabled
1F	0001 1111	BEP?			Branch on Even Parity (Changed for CPU6? Branch on AH at interrupt level 1 bit 0 set. See instructions B6 and C6)

20	0010 0000	INR	Byte Register in high nibble, unsigned constant in low nibble		Increment byte of explicit register by 1 + constant
21	0010 0001	DCR	Byte Register in high nibble, unsigned constant in low nibble		Decrement byte of explicit register by 1 + constant
22	0010 0010	CLR	Byte Register in high nibble, unsigned constant in low nibble		Clear byte of explicit register to constant
23	0010 0011	IVR	Byte Register in high nibble, unsigned constant in low nibble		Invert byte of explicit register, constant 1 is negate
24	0010 0100	SRR	Byte Register in high nibble, unsigned constant in low nibble		Arithmetic Shift byte of explicit register right by 1 + constant
25	0010 0101	SLR	Byte Register in high nibble, unsigned constant in low nibble		Shift byte of explicit register left by 1 + constant
26	0010 0110	RRR	Byte Register in high nibble, unsigned constant in low nibble		Rotate byte of explicit register right by 1 + constant (wraps through carry)
27	0010 0111	RLR	Byte Register in high nibble, unsigned constant in low nibble		Rotate byte of explicit register left by 1 + constant (wraps through carry)
28	0010 1000	INAL			Increment byte of implicit AL register
29	0010 1001	DCAL			Decrement byte of implicit AL register
2A	0010 1010	CLAL			Clear byte of implicit AL register
2B	0010 1011	IVAL			Invert byte of implicit AL register
2C	0010 1100	SRAL			Shift byte of implicit AL register right
2D	0010 1101	SLAL			Shift byte of implicit AL register left
2E	0010 1110	*See chart below	*See chart below		Special two byte instruction
2F	0010 1111	*See chart below	*See chart below		Special two byte instruction

30	0011 0000	INR	Word Register in high nibble, unsigned constant in low nibble		Increment word of explicit register by 1 + constant. Using an odd register will operate on memory.
31	0011 0001	DCR	Word Register in high nibble, unsigned constant in low nibble		Decrement word of explicit register by 1 + constant. Using an odd register will operate on memory.
32	0011 0010	CLR	Word Register in high nibble, unsigned constant in low nibble		Clear word of explicit register to constant. Using an odd register will operate on memory.
33	0011 0011	IVR	Word Register in high nibble, unsigned constant in low nibble		Invert word of explicit register, constant 1 is negate. Using an odd register will operate on memory.
34	0011 0100	SRR	Word Register in high nibble, unsigned constant in low nibble		Arithmetic Shift word of explicit register right by 1 + constant. Using an odd register will operate on memory.
35	0011 0101	SLR	Word Register in high nibble, unsigned constant in low nibble		Shift word of explicit register left by 1 + constant. Using an odd register will operate on memory.
36	0011 0110	RRR	Word Register in high nibble, unsigned constant in low nibble		Rotate word of explicit register right (wraps through carry) by 1 + constant. Using an odd register will operate on memory.
37	0011 0111	RLR	Word Register in high nibble, unsigned constant in low nibble		Rotate word of explicit register left (wraps through carry) by 1 + constant. Using an odd register will operate on memory.
38	0011 1000	INAW			Increment word of implicit AW register
39	0011 1001	DCAW			Decrement word of implicit AW register
3A	0011 1010	CLAW			Clear word of implicit AW register
3B	0011 1011	IVAW			Invert word of implicit AW register
3C	0011 1100	SRAW			Shift word of implicit AW register right
3D	0011 1101	SLAW			Shift word of implicit AW register left
3E	0011 1110	INX			Increment word of implicit X register
3F	0011 1111	DCX			Decrement word of implicit X register

40	0100 0000	ADD	Byte register, Byte register		Add bytes of two explicit registers (left plus right stored in right)
41	0100 0001	SUB	Byte register, Byte register		Subtract bytes of two explicit registers (left minus right stored in right)
42	0100 0010	AND	Byte register, Byte register		AND bytes of two explicit registers (left AND right stored in right)
43	0100 0011	ORI	Byte register, Byte register		OR bytes of two explicit registers (left OR right stored in right)
44	0100 0100	ORE	Byte register, Byte register		XOR bytes of two explicit registers (left XOR right stored in right)
45	0100 0101	XFR	Byte register, Byte register		Copy byte of one explicit register into other explicit register (left into right)
46	0100 0110	*See chart below	*See chart below		Special two byte instruction
47	0100 0111	*See chart below	*See chart below		Special two byte instruction
48	0100 1000	AABL			Add bytes of implicit AL and BL (AL plus BL stored in BL)
49	0100 1001	SABL			Subtract bytes of implicit AL and BL (AL minus BL stored in BL)
4A	0100 1010	NABL			AND bytes of implicit AL and BL (AL AND BL stored in BL)
4B	0100 1011	XAXL			Transfer byte of implicit AL into XL
4C	0100 1100	XAYL			Transfer byte of implicit AL into YL
4D	0100 1101	XABL			Transfer byte of implicit AL into BL
4E	0100 1110	XAZL			Transfer byte of implicit AL into ZL
4F	0100 1111	XASL			Transfer byte of implicit AL into SL

50	0101 0000	ADD	Word Register, Word Register		Add word of two explicit registers (left plus right stored in right). Using an odd register for either operand will operate on memory.
51	0101 0001	SUB	Word Register, Word Register		Subtract word of two explicit registers (left minus right stored in right). Using an odd register for either operand will operate on memory.
52	0101 0010	AND	Word Register, Word Register		AND word of two explicit registers (left AND right stored in right). Using an odd register for either operand will operate on memory.
53	0101 0011	ORI	Word Register, Word Register		OR word of two explicit registers (left OR right stored in right). Using an odd register for either operand will operate on memory.
54	0101 0100	ORE	Word Register, Word Register		XOR word of two explicit registers (left XOR right stored in right). Using an odd register for either operand will operate on memory.
55	0101 0101	XFR	Word Register, Word Register		Copy word of one explicit register into other explicit register (left into right). Using an odd register for either operand will operate on memory.
56	0101 0110	??			Set high bit in internal status register. (possibly trap on buffer overflow on string instructions)
57	0101 0111	??			Clear high bit in internal status register. (possibly trap on buffer overflow on string instructions)
58	0101 1000	AABW			Add word of implicit AW and BW (AW plus BW stored in BW)
59	0101 1001	SABW			Subtract word of implicit AW and BW (AW minus BW stored in BW)
5A	0101 1010	NABW			AND word of implicit AW and BW (AW AND BW stored in BW)
5B	0101 1011	XAXW			Transfer word of implicit AW into XW
5C	0101 1100	XAYW			Transfer word of implicit AW into YW
5D	0101 1101	XABW			Transfer word of implicit AW into BW
5E	0101 1110	XAZW			Transfer word of implicit AW into ZW
5F	0101 1111	XASW			Transfer word of implicit AW into SW

60	0110 0000	LDXW	#Literal	#Literal	Load immediate address into full word X
61	0110 0001	LDXW	Direct	Direct	Load direct address into full word X
62	0110 0010	LDXW	[Indirect]	[Indirect]	Load indirect address into full word X
63	0110 0011	LDXW	PC+N		Load direct Program Counter offset by N address into full word X
64	0110 0100	LDXW	[PC+N]		Load indirect Program Counter offset by N address into full word X
65	0110 0101	LDXW	Word Register, Mod.	Offset	Load indexed mode register into full word X
66	0110 0110	JSYS	#Literal		System Call. Pushes CCR + Page Table Map, Current IPL, X, X <- PC, pushes literal as argument. Clears the Page Table Map and jumps to 0x0100. See also RSYS.
67	0110 0111	*See chart below	*See chart below		Special two byte instruction
68	0110 1000	STXW	Store Location	Store Location	Store word of XW register into PC address (PC)+ <- X. Opposite of 60
69	0110 1001	STXW	Direct	Direct	Store word of XW register into direct address
6A	0110 1010	STXW	[Indirect]	[Indirect]	Store word of XW register into indirect address
6B	0110 1011	STXW	PC+N		Store word of XW register into direct Program Counter offset by N address
6C	0110 1100	STXW	[PC+N]		Store word of XW register into indirect Program Counter offset by N address
6D	0110 1101	STXW	Word Register, Mod.	Offset	Store word of XW register into indexed register
6E	0110 1110	LDCC	Direct	Direct	Load CCR with byte at address
6F	0110 1111	STCC	Direct	Direct	Store CCR to address

70	0111 0000	JMP	#Literal	#Literal	Jump to literal address (Not possible?)
71	0111 0001	JMP	Direct	Direct	Jump to direct address
72	0111 0010	JMP	[Indirect]	[Indirect]	Jump to indirect address
73	0111 0011	JMP	PC+N		Jump to direct Program Counter offset by N address
74	0111 0100	JMP	[PC+N]		Jump to indirect Program Counter offset by N address
75	0111 0101	JMP	Word Register, Mod.	Offset	Jump to indexed mode register
76	0111 0110	??			Enable Parity Checking
77	0111 0111	MULU	Word Register, Word Register		Unsigned multiply Using an odd register for either operand will operate on memory. 32 bit result is stored in adjacent registers.
78	0111 1000	DIVU	Word Register, Word Register		Unsigned divide Using an odd register for either operand will operate on memory. Link flag is set for zero remainder. Result stored as remainder, quotient in adjacent 16 bit registers.
79	0111 1001	JSR	Direct	Direct	Jump to subroutine at direct address (Careful with JSR, check S register)
7A	0111 1010	JSR	[Indirect]	[Indirect]	Jump to subroutine at indirect address
7B	0111 1011	JSR	PC+N		Jump to subroutine at Program Counter offset by N address
7C	0111 1100	JSR	[PC+N]		Jump to subroutine at indirect Program Counter offset by N address
7D	0111 1101	JSR	Word Register, Mod.	Offset	Jump to subroutine at indexed mode register
7E	0111 1110	PUSH	First Byte Register in high nibble, Count - 1 in low nibble		Push multiple 8 bit registers to the stack. Registers are pushed from last (highest) to first
7F	0111 1111	POP	First Byte Register in high nibble, Count - 1 in low nibble		Pop multiple 8 bit registers from the stack. Registers are popped from first (lowest) to last

80	1000 0000	LDAL	#Literal		Load literal address into byte of AL register (Pretty sure 2-byte opcode)
81	1000 0001	LDAL	Direct		Load direct address into byte of AL register (Pretty sure 2-byte opcode)
82	1000 0010	LDAL	[Indirect]		Load indirect address into byte of AL register (Pretty sure 2-byte opcode)
83	1000 0011	LDAL	PC+N		Load direct Program Counter offset by N address into byte of AL register
84	1000 0100	LDAL	[PC+N]		Load indirect Program Counter offset by N address into byte of AL register
85	1000 0101	LDAL	Word Register, Mod.	Offset	Load indexed register into byte of AL register
86	1000 0110	??			Disable Parity Checking
87	1000 0111	??			Illegal?
88	1000 1000	LALA			Load byte from memory address stored in implicit AW into AL register
89	1000 1001	LALB			Load byte from memory address stored in implicit BW into AL register
8A	1000 1010	LALX			Load byte from memory address stored in implicit XW into AL register
8B	1000 1011	LALY			Load byte from memory address stored in implicit YW into AL register
8C	1000 1100	LALZ			Load byte from memory address stored in implicit ZW into AL register
8D	1000 1101	LALS			Load byte from memory address stored in implicit S into AL register
8E	1000 1110	LALC			Load byte from memory address stored in implicit C into AL register
8F	1000 1111	LALP			Load byte from memory address stored in implicit P into AL register

90	1001 0000	LDAW	#Literal	#Literal	Load literal address into full word of AW register
91	1001 0001	LDAW	Direct	Direct	Load direct address into full word of AW register
92	1001 0010	LDAW	[Indirect]	[Indirect]	Load indirect address into full word of AW register
93	1001 0011	LDAW	PC+N		Load direct Program Counter offset by N address into full word of AW register
94	1001 0100	LDAW	[PC+N]		Load indirect Program Counter offset by N address into full word of AW register
95	1001 0101	LDAW	Word Register, Mod.	Offset	Load indexed register into full word of AW register
96	1001 0110	??			Set even parity?
97	1001 0111	??			Illegal?
98	1001 1000	LAWA			Load word from memory address stored in implicit AW into AW register
99	1001 1001	LAWB			Load word from memory address stored in implicit BW into AW register
9A	1001 1010	LAWX			Load word from memory address stored in implicit XW into AW register
9B	1001 1011	LAWY			Load word from memory address stored in implicit YW into AW register
9C	1001 1100	LAWZ			Load word from memory address stored in implicit ZW into AW register
9D	1001 1101	LAWS			Load word from memory address stored in implicit S into AW register
9E	1001 1110	LAWC			Load word from memory address stored in implicit C into AW register
9F	1001 1111	LAWP			Load word from memory address stored in implicit P into AW register

A0	1010 0000	STAL	Store Location		Store byte of AL register into PC address (PC)+ <- AL. Opposite of 80
A1	1010 0001	STAL	Direct	Direct	Store byte of AL register into direct address
A2	1010 0010	STAL	[Indirect]	[Indirect]	Store byte of AL register into indirect address
A3	1010 0011	STAL	PC+N		Store byte of AL register into direct Program Counter offset by N address
A4	1010 0100	STAL	[PC+N]		Store byte of AL register into indirect Program Counter offset by N address
A5	1010 0101	STAL	Word Register, Mod.	Offset	Store byte of AL register into indexed register
A6	1010 0110	??			Set odd parity?
A7	1010 0111	??			Illegal?
A8	1010 1000	SALA			Store byte from implicit AW register to memory address stored in AW
A9	1010 1001	SALB			Store byte from implicit AW register to memory address stored in BW
AA	1010 1010	SALX			Store byte from implicit AW register to memory address stored in XW
AB	1010 1011	SALY			Store byte from implicit AW register to memory address stored in YW
AC	1010 1100	SALZ			Store byte from implicit AW register to memory address stored in ZW
AD	1010 1101	SALS			Store byte from implicit AW register to memory address stored in S
AE	1010 1110	SALC			Store byte from implicit AW register to memory address stored in C
AF	1010 1111	SALP			Store byte from implicit AW register to memory address stored in P

B0	1011 0000	STAW	Store Location	Store Location	Store word of AW register into PC address (PC)+ <- AW. Opposite of 90
B1	1011 0001	STAW	Direct	Direct	Store word of AW register into direct address
B2	1011 0010	STAW	[Indirect]	[Indirect]	Store word of AW register into indirect address
B3	1011 0011	STAW	PC+N		Store word of AW register into direct Program Counter offset by N address
B4	1011 0100	STAW	[PC+N]		Store word of AW register into indirect Program Counter offset by N address
B5	1011 0101	STAW	Word Register, Mod.	Offset	Store word of AW register into indexed register
B6	1011 0110	??			Writes -1 to AH at interrupt level 1. See instructions C6 and 1F
B7	1011 0111	??			Illegal?
B8	1011 1000	SAWA			Store word from implicit AW register to memory address stored in AW
B9	1011 1001	SAWB			Store word from implicit AW register to memory address stored in BW
BA	1011 1010	SAWX			Store word from implicit AW register to memory address stored in XW
BB	1011 1011	SAWY			Store word from implicit AW register to memory address stored in YW
BC	1011 1100	SAWZ			Store word from implicit AW register to memory address stored in ZW
BD	1011 1101	SAWS			Store word from implicit AW register to memory address stored in S
BE	1011 1110	SAWC			Store word from implicit AW register to memory address stored in C
BF	1011 1111	SAWP			Store word from implicit AW register to memory address stored in P

C0	1100 0000	LDBL	#Literal		Load literal address into byte of BL register (Pretty sure 2-byte opcode)
C1	1100 0001	LDBL	Direct		Load direct address into byte of BL register (Pretty sure 2-byte opcode)
C2	1100 0010	LDBL	[Indirect]		Load indirect address into byte of BL register (Pretty sure 2-byte opcode)
C3	1100 0011	LDBL	PC+N		Load direct Program Counter offset by N address into byte of BL register
C4	1100 0100	LDBL	[PC+N]		Load indirect Program Counter offset by N address into byte of BL register
C5	1100 0101	LDBL	Word Register, Mod.	Offset	Load indexed register into byte of BL register
C6	1100 0110	??			Writes 0 to AH at interrupt level 1. See instructions B6 and 1F
C7	1100 0111	??			Illegal
C8	1100 1000	LBLA			Load byte from memory address stored in implicit AW into BL register
C9	1100 1001	LBLB			Load byte from memory address stored in implicit BW into BL register
CA	1100 1010	LBLX			Load byte from memory address stored in implicit XW into BL register
CB	1100 1011	LBLY			Load byte from memory address stored in implicit YW into BL register
CC	1100 1100	LBLZ			Load byte from memory address stored in implicit ZW into BL register
CD	1100 1101	LBLS			Load byte from memory address stored in implicit S into BL register
CE	1100 1110	LBLC			Load byte from memory address stored in implicit C into BL register
CF	1100 1111	LBLP			Load byte from memory address stored in implicit P into BL register

D0	1101 0000	LDBW	#Literal	#Literal	Load literal address into full word of BW register
D1	1101 0001	LDBW	Direct	Direct	Load direct address into full word of BW register
D2	1101 0010	LDBW	[Indirect]	[Indirect]	Load indirect address into full word of BW register
D3	1101 0011	LDBW	PC+N		Load direct Program Counter offset by N address into full word of BW register
D4	1101 0100	LDBW	[PC+N]		Load indirect Program Counter offset by N address into full word of BW register
D5	1101 0101	LDBW	Word Register, Mod.	Offset	Load indexed register into full word of BW register
D6	1101 0110	*See chart below	*See chart below		Special two byte instruction
D7	1101 0111	??	Register		Stores AW into any register in register file
D8	1101 1000	LBWA			Load word from memory address stored in implicit AW into BW register
D9	1101 1001	LBWB			Load word from memory address stored in implicit BW into BW register
DA	1101 1010	LBWX			Load word from memory address stored in implicit XW into BW register
DB	1101 1011	LDBW			Load word from memory address stored in implicit YW into BW register
DC	1101 1100	LBWZ			Load word from memory address stored in implicit ZW into BW register
DD	1101 1101	LBWS			Load word from memory address stored in implicit S into BW register
DE	1101 1110	LBWC			Load word from memory address stored in implicit C into BW register
DF	1101 1111	LBWP			Load word from memory address stored in implicit P into BW register

E0	1110 0000	STBL	Store Location		Store byte of BL register into PC address (PC)+ <- BL. This is the opposite of C0
E1	1110 0001	STBL	Direct	Direct	Store byte of BL register into direct address
E2	1110 0010	STBL	[Indirect]	[Indirect]	Store byte of BL register into indirect address
E3	1110 0011	STBL	PC+N		Store byte of BL register into direct Program Counter offset by N address
E4	1110 0100	STBL	[PC+N]		Store byte of BL register into indirect Program Counter offset by N address
E5	1110 0101	STBL	Word Register, Mod.	Offset	Store byte of BL register into indexed register
E6	1110 0110	??	Register		Load AW from any register in register file?
E7	1110 0111	??			Illegal?
E8	1110 1000	SBLA			Store byte from implicit BL register to memory address stored in AW
E9	1110 1001	SBLB			Store byte from implicit BL register to memory address stored in BW
EA	1110 1010	SBLX			Store byte from implicit BL register to memory address stored in XW
EB	1110 1011	SBLY			Store byte from implicit BL register to memory address stored in YW
EC	1110 1100	SBLZ			Store byte from implicit BL register to memory address stored in ZW
ED	1110 1101	SBLS			Store byte from implicit BL register to memory address stored in S
EE	1110 1110	SBLC			Store byte from implicit BL register to memory address stored in C
EF	1110 1111	SBLP			Store byte from implicit BL register to memory address stored in P

F0	1111 0000	STBW	Store Location	Store Location	Store word of BW register into PC address (PC)+ <- BW. This is the opposite of D0
F1	1111 0001	STBW	Direct	Direct	Store word of BW register into direct address
F2	1111 0010	STBW	[Indirect]	[Indirect]	Store word of BW register into indirect address
F3	1111 0011	STBW	PC+N		Store word of BW register into direct Program Counter offset by N address
F4	1111 0100	STBW	[PC+N]		Store word of BW register into indirect Program Counter offset by N address
F5	1111 0101	STBW	Word Register, Mod.	Offset	Store word of BW register into indexed register
F6	1111 0110	??			Something to do with page table management
F7	1111 0111	??			Copies AW bytes of memory from BW to YW
F8	1111 1000	SBWA			Store word from implicit BW register to memory address stored in AW
F9	1111 1001	SBWB			Store word from implicit BW register to memory address stored in BW
FA	1111 1010	SBWX			Store word from implicit BW register to memory address stored in XW
FB	1111 1011	SBWY			Store word from implicit BW register to memory address stored in YW
FC	1111 1100	SBWZ			Store word from implicit BW register to memory address stored in ZW
FD	1111 1101	SBWS			Store word from implicit BW register to memory address stored in S
FE	1111 1110	SBWC			Store word from implicit BW register to memory address stored in C
FF	1111 1111	SBWP			Store word from implicit BW register to memory address stored in P

3x Extended Addressing

If an odd register is specified for a 3x instruction, the operation is on memory. Note that this is still very much WIP.

For a register specifier of 1, the effective address is the direct address of the word following. For other odd registers, the effective address is indexed from the relative 16 bit register.

Register Nibble	Meaning	Example	Description
1	Direct	`32 12 1234`	Clear word at address 1234 to 2
3	Indexed B	`32 32 1234`	Clear word at address 1234 + B to 2
5	Indexed X	`32 52 1234`	Clear word at address 1234 + X to 2
7	Indexed Y	`32 72 1234`	Clear word at address 1234 + Y to 2
9	Indexed Z	`32 92 1234`	Clear word at address 1234 + Z to 2
b	Indexed S	`32 B2 1234`	Clear word at address 1234 + S to 2
d	Indexed C	`32 D2 1234`	Possibly illegal. Clear word at address 1234 + C to 2
f	Indexed P	`32 F2 1234`	Clear word at address 1234 + P to 2

5x Extended Addressing

If either of the register nibbles are odd for a 5x instruction, then extended addressing modes will be used for the instruction. The src and dest registers are obtained by stripping out the low bit of their nibbles. Note that this is still very much WIP and needs to be verified on hardware.

Left Register odd, Right Register even - dest <- src op literal
Left Register even, Right Register odd - dest <- src op (direct)
Left Register odd, Right Register odd - dest <- index(src) op dest

Note that subtraction, division and XFR vary from the register to register variants. Examples are given in the table below.

Opcode	Operation	High nibble (src)	Low nibble (dest)	Meaning
51	SUB	Even	Odd	dest <- direct - src
51	SUB	Odd	Odd	dest <- index(src) - dest
55	XFR	Odd	Even	dest <- #literal
78	DIV	Even	Odd	dest <- src / direct
78	DIV	Odd	Odd	dest <- dest / index(src)

2e Instructions

These instructions are of the form 2E ssssmmnn where ssss is the instruction selector and mm is the addressing mode of the first operand and nn is the addressing mode of the second operand.

Addressing modes

This section describes the addressing modes for the 2e instruction. This is very much WIP. These modes are shared with other instructions.

For mode 2, the microcode indicates whether the register will be in the high nibble or low nibble of the relevant byte.

Mode	Function	Description
0	EA <- (PC)	Direct
1	EA <- imm8/imm16 + r1 + r2 (if r2 is not AW) r1/r2 are 16 bit registers indicated in byte following instruction high and low nibble respectively. imm8/imm16 follows r1/r2. Imm16 is used if r1 is odd (the word register is still used as the index)
2	EA <- R, R in high or low nibble of byte at PC determined by microcode	Register
3	EA <- PC	Literal (illegal when address must be specified). Size provided in microcode.

Selector

Selector	Opcode	Operand 1	Operand 2	Description
0	WPF	Low 3 bits: page table map. High 5 bits: count	Address	Write Page File - write count page table entries with page table map from Operand 2 address
1	RPF	Low 3 bits: page table map. High 5 bits: count	Address	Read Page File - read count page table entries with page table map to Operand 2 address. Set top bit from MSR
2	WPF1	Low 3 bits: page table map. High 5 bits: Page table index	Address	Write Page File 1 entry from Operand 2 address
3	RPF1	Low 3 bits: page table map. High 5 bits: Page table index	Address	Read Page File 1 entry to Operand 2 address. Set top bit from MSR
4	WPFH	Low 3 bits: page table map. High 5 bits: Page table index	Address	Write Page File High. Writes `32-index` entries from Operand 2 address
5	RPFH	Low 3 bits: page table map. High 5 bits: Page table index	Address	Read Page File High. Reads `32-index` entries to Operand 2 address. Set top bit from MSR

2f Instructions

These instructions are mainly concerning DMA. There are ten DMA instructions. The instructions are of the form 2e rs where r is a register and s is the instruction selector.

Selector	Opcode	Description
0	LDDMAA	Load DMA Address from word register
1	STDMAA	Store DMA Address to word register
2	LDDMAC	Load DMA Count from word register
3	STDMAC	Store DMA Count to word register
4	SETDMAM	Set DMA mode. Mode is constant in register nibble
5	SETDMAMR	Set DMA mode. Mode is read from register in register nibble. Will always use the low byte even if a high byte register is provided
6	EDMA	Enable DMA
7	DDMA	Disable DMA
8	LDDMAMAP	Load low three bits of Internal Status Register from register. Will always use the low byte even if a high byte register is provided
9	STDMAMAP	Store Internal Status Register to register. This instruction is buggy and will only store some of the bits depending on the register provided (the status register is masked on the inverse of the register number). Best results will be with AH. Will always use the low byte even if a high byte register is provided

46 Instructions

These instructions are big number operations. The instruction form is 46 llllkkkk ssssmmnn where l is the size of operand 1, k is the size of operand 2, s is the operation selection (so far 0 is +, 1 is -), m and n are CPU6 extended instruction addressing modes. The first operand is the source, the second is the destination.

Selector	Opcode	Description
0	ADDBIG	Adds two big numbers. Dest = Src + Dest
1	SUBBIG	Subtracts two big numbers. Dest = Src - Dest
2	CMPBIG	Set flags based on subtraction
3	XFRBIG	Assigns a big number
4	NEGBIG	Negates a big number
5	MULBIG	Multiplies two big numbers (signed). Zero results where one operand is negative are unreliable
6	DIVBIG	Divides two big numbers (signed). Remainder is not stored
7	DIVBIGR	Divides two big numbers (signed). Remainder is written to address pointed to by AW. Link flag is set for zero remainder
8	IBASECONV	Base string to Big number. Base can be from 2 to 17. (TODO - describe how base is provided - similar to OBASECONV)
9	OBASECONV	Big number to Base string. Base can be from 2 to 17. Operand 1 is destination, Operand 2 is source. Base is length field of Operand 1 (field holds Base - 2). Operand 1 length is provided in AL. BL provides padding byte. AW holds address of result following operation. Result is formatted, `@` in destination will be replaced by result. `#` in destination is padding marker, result will be zero filled until marker, from marker on result will be filled with padding byte. Other bytes in destination are left as is.

47 and 67 Instructions

These instructions appear to operate on strings or memory blocks. The general form is 47 ssssmmnn followed by the operands. m and n are the CPU6 addressing modes. 47 4x and 47 8x have an additional literal byte length argument (length of block - 1). 47 2x has two additional arguments,

67 instructions are identical to 47 instructions, except when relevant, they take their length argument in register AL (WIP, it is unknown if 67 instructions are limited to 8bit lengths)

Selector	Opcode	1st Operand	2nd Operand	3rd Operand	4th Operand	Description
0	binload	BaseAddress	record			Implements most of the Centurion binary record format in Microcode.
1	strcmp?
2	condcpy?	MaxCount - 1	(implicit) byte to match	Src	Dest	Copies from Source to Dest until matching byte is found (can be used as strcpy). Sets Fault if no match found. Sets Y to match in Src. Sets Z to match in Dest
3
4	memcpy	Count - 1	Count Length any mode	count length memory		copy block of memory from first argument to second argument
5
6
7
8	memcmp	Count - 1	Count Length any mode	count length memory		compare two blocks of memory
9	memset	Count - 1	Single Byte	count length memory		copies first arg repeated to second arg

D6 Instruction

A 16 bit move/store that uses the inverse of 5x Extended Addressing. Takes a operand byte with register nibbles. The lower bit of each register nibble selects an addressing mode