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Add RTLIL "buffered-normalized mode" and improve "bufnorm" pass
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Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
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@clairexen @povik
clairexen authored and povik committed Sep 17, 2024
1 parent 8bb70ba commit 8011938
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Showing 5 changed files with 238 additions and 13 deletions.
27 changes: 19 additions & 8 deletions backends/rtlil/rtlil_backend.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -118,13 +118,17 @@ void RTLIL_BACKEND::dump_sigspec(std::ostream &f, const RTLIL::SigSpec &sig, boo
}
}

void RTLIL_BACKEND::dump_wire(std::ostream &f, std::string indent, const RTLIL::Wire *wire)
void RTLIL_BACKEND::dump_wire(std::ostream &f, std::string indent, const RTLIL::Wire *wire, bool flag_d)
{
for (auto &it : wire->attributes) {
f << stringf("%s" "attribute %s ", indent.c_str(), it.first.c_str());
dump_const(f, it.second);
f << stringf("\n");
}
if (flag_d && wire->driverCell) {
f << stringf("%s" "driver %s %s\n", indent.c_str(),
wire->driverCell->name.c_str(), wire->driverPort.c_str());
}
f << stringf("%s" "wire ", indent.c_str());
if (wire->width != 1)
f << stringf("width %d ", wire->width);
Expand Down Expand Up @@ -298,7 +302,7 @@ void RTLIL_BACKEND::dump_conn(std::ostream &f, std::string indent, const RTLIL::
f << stringf("\n");
}

void RTLIL_BACKEND::dump_module(std::ostream &f, std::string indent, RTLIL::Module *module, RTLIL::Design *design, bool only_selected, bool flag_m, bool flag_n)
void RTLIL_BACKEND::dump_module(std::ostream &f, std::string indent, RTLIL::Module *module, RTLIL::Design *design, bool only_selected, bool flag_m, bool flag_n, bool flag_d)
{
bool print_header = flag_m || design->selected_whole_module(module->name);
bool print_body = !flag_n || !design->selected_whole_module(module->name);
Expand Down Expand Up @@ -335,7 +339,7 @@ void RTLIL_BACKEND::dump_module(std::ostream &f, std::string indent, RTLIL::Modu
if (!only_selected || design->selected(module, it)) {
if (only_selected)
f << stringf("\n");
dump_wire(f, indent + " ", it);
dump_wire(f, indent + " ", it, flag_d);
}

for (auto it : module->memories)
Expand Down Expand Up @@ -384,7 +388,7 @@ void RTLIL_BACKEND::dump_module(std::ostream &f, std::string indent, RTLIL::Modu
f << stringf("%s" "end\n", indent.c_str());
}

void RTLIL_BACKEND::dump_design(std::ostream &f, RTLIL::Design *design, bool only_selected, bool flag_m, bool flag_n)
void RTLIL_BACKEND::dump_design(std::ostream &f, RTLIL::Design *design, bool only_selected, bool flag_m, bool flag_n, bool flag_d)
{
int init_autoidx = autoidx;

Expand All @@ -410,7 +414,7 @@ void RTLIL_BACKEND::dump_design(std::ostream &f, RTLIL::Design *design, bool onl
if (!only_selected || design->selected(module)) {
if (only_selected)
f << stringf("\n");
dump_module(f, "", module, design, only_selected, flag_m, flag_n);
dump_module(f, "", module, design, only_selected, flag_m, flag_n, flag_d);
}
}

Expand Down Expand Up @@ -456,7 +460,7 @@ struct RTLILBackend : public Backend {

log("Output filename: %s\n", filename.c_str());
*f << stringf("# Generated by %s\n", yosys_version_str);
RTLIL_BACKEND::dump_design(*f, design, selected, true, false);
RTLIL_BACKEND::dump_design(*f, design, selected, true, false, false);
}
} RTLILBackend;

Expand Down Expand Up @@ -493,6 +497,9 @@ struct DumpPass : public Pass {
log(" -n\n");
log(" only dump the module headers if the entire module is selected\n");
log("\n");
log(" -d\n");
log(" include driver cell and port info on wires in dump format\n");
log("\n");
log(" -o <filename>\n");
log(" write to the specified file.\n");
log("\n");
Expand All @@ -503,7 +510,7 @@ struct DumpPass : public Pass {
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
std::string filename;
bool flag_m = false, flag_n = false, append = false;
bool flag_m = false, flag_n = false, flag_d = false, append = false;

size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)
Expand All @@ -527,6 +534,10 @@ struct DumpPass : public Pass {
flag_n = true;
continue;
}
if (arg == "-d") {
flag_d = true;
continue;
}
break;
}
extra_args(args, argidx, design);
Expand All @@ -548,7 +559,7 @@ struct DumpPass : public Pass {
f = &buf;
}

RTLIL_BACKEND::dump_design(*f, design, true, flag_m, flag_n);
RTLIL_BACKEND::dump_design(*f, design, true, flag_m, flag_n, flag_d);

if (!empty) {
delete f;
Expand Down
6 changes: 3 additions & 3 deletions backends/rtlil/rtlil_backend.h
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Original file line number Diff line number Diff line change
Expand Up @@ -34,16 +34,16 @@ namespace RTLIL_BACKEND {
void dump_const(std::ostream &f, const RTLIL::Const &data, int width = -1, int offset = 0, bool autoint = true);
void dump_sigchunk(std::ostream &f, const RTLIL::SigChunk &chunk, bool autoint = true);
void dump_sigspec(std::ostream &f, const RTLIL::SigSpec &sig, bool autoint = true);
void dump_wire(std::ostream &f, std::string indent, const RTLIL::Wire *wire);
void dump_wire(std::ostream &f, std::string indent, const RTLIL::Wire *wire, bool flag_d = false);
void dump_memory(std::ostream &f, std::string indent, const RTLIL::Memory *memory);
void dump_cell(std::ostream &f, std::string indent, const RTLIL::Cell *cell);
void dump_proc_case_body(std::ostream &f, std::string indent, const RTLIL::CaseRule *cs);
void dump_proc_switch(std::ostream &f, std::string indent, const RTLIL::SwitchRule *sw);
void dump_proc_sync(std::ostream &f, std::string indent, const RTLIL::SyncRule *sy);
void dump_proc(std::ostream &f, std::string indent, const RTLIL::Process *proc);
void dump_conn(std::ostream &f, std::string indent, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right);
void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module, RTLIL::Design *design, bool only_selected, bool flag_m = true, bool flag_n = false);
void dump_design(std::ostream &f, RTLIL::Design *design, bool only_selected, bool flag_m = true, bool flag_n = false);
void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module, RTLIL::Design *design, bool only_selected, bool flag_m = true, bool flag_n = false, bool flag_d = false);
void dump_design(std::ostream &f, RTLIL::Design *design, bool only_selected, bool flag_m = true, bool flag_n = false, bool flag_d = false);
}

YOSYS_NAMESPACE_END
Expand Down
133 changes: 133 additions & 0 deletions kernel/rtlil.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -21,6 +21,7 @@
#include "kernel/macc.h"
#include "kernel/celltypes.h"
#include "kernel/binding.h"
#include "kernel/sigtools.h"
#include "frontends/verilog/verilog_frontend.h"
#include "frontends/verilog/preproc.h"
#include "backends/rtlil/rtlil_backend.h"
Expand Down Expand Up @@ -3564,6 +3565,104 @@ void RTLIL::Cell::unsetPort(const RTLIL::IdString& portname)
}
}

void RTLIL::Design::bufNormalize(bool enable)
{
if (!enable)
{
if (!flagBufferedNormalized)
return;

for (auto module : modules()) {
module->bufNormQueue.clear();
for (auto wire : module->wires()) {
wire->driverCell = nullptr;
wire->driverPort = IdString();
}
}
return;
}

if (!flagBufferedNormalized)
{
for (auto module : modules())
{
for (auto cell : module->cells())
for (auto &conn : cell->connections()) {
if (!cell->output(conn.first) || GetSize(conn.second) == 0)
continue;
if (conn.second.is_wire()) {
Wire *wire = conn.second.as_wire();
log_assert(wire->driverCell == nullptr);
wire->driverCell = cell;
wire->driverPort = conn.first;
} else {
pair<RTLIL::Cell*, RTLIL::IdString> key(cell, conn.first);
module->bufNormQueue.insert(key);
}
}
}

flagBufferedNormalized = true;
}

for (auto module : modules())
module->bufNormalize();
}

void RTLIL::Module::bufNormalize()
{
if (!design->flagBufferedNormalized)
return;

while (GetSize(bufNormQueue))
{
pool<pair<RTLIL::Cell*, RTLIL::IdString>> queue;
bufNormQueue.swap(queue);

pool<Wire*> outWires;
for (auto &conn : connections())
for (auto &chunk : conn.first.chunks())
if (chunk.wire) outWires.insert(chunk.wire);

SigMap sigmap(this);
new_connections({});

for (auto &key : queue)
{
Cell *cell = key.first;
const IdString &portname = key.second;
const SigSpec &sig = cell->getPort(portname);
if (GetSize(sig) == 0) continue;

if (sig.is_wire()) {
Wire *wire = sig.as_wire();
log_assert(wire->driverCell == nullptr);
wire->driverCell = cell;
wire->driverPort = portname;
continue;
}

for (auto &chunk : sig.chunks())
if (chunk.wire) outWires.insert(chunk.wire);

Wire *wire = addWire(NEW_ID, GetSize(sig));
sigmap.add(sig, wire);
cell->setPort(portname, wire);

// FIXME: Move init attributes from old 'sig' to new 'wire'
}

for (auto wire : outWires)
{
SigSpec outsig = wire, insig = sigmap(wire);
for (int i = 0; i < GetSize(wire); i++)
if (insig[i] == outsig[i])
insig[i] = State::Sx;
addBuf(NEW_ID, insig, outsig);
}
}
}

void RTLIL::Cell::setPort(const RTLIL::IdString& portname, RTLIL::SigSpec signal)
{
auto r = connections_.insert(portname);
Expand All @@ -3583,6 +3682,40 @@ void RTLIL::Cell::setPort(const RTLIL::IdString& portname, RTLIL::SigSpec signal
log_backtrace("-X- ", yosys_xtrace-1);
}

while (module->design && module->design->flagBufferedNormalized && output(portname))
{
pair<RTLIL::Cell*, RTLIL::IdString> key(this, portname);

if (conn_it->second.is_wire()) {
Wire *w = conn_it->second.as_wire();
if (w->driverCell == this && w->driverPort == portname) {
w->driverCell = nullptr;
w->driverPort = IdString();
}
}

if (GetSize(signal) == 0) {
module->bufNormQueue.erase(key);
break;
}

if (!signal.is_wire()) {
module->bufNormQueue.insert(key);
break;
}

Wire *w = signal.as_wire();
if (w->driverCell != nullptr) {
pair<RTLIL::Cell*, RTLIL::IdString> other_key(w->driverCell, w->driverPort);
module->bufNormQueue.insert(other_key);
}
w->driverCell = this;
w->driverPort = portname;

module->bufNormQueue.erase(key);
break;
}

conn_it->second = std::move(signal);
}

Expand Down
9 changes: 9 additions & 0 deletions kernel/rtlil.h
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Original file line number Diff line number Diff line change
Expand Up @@ -1066,6 +1066,9 @@ struct RTLIL::Design
pool<RTLIL::Monitor*> monitors;
dict<std::string, std::string> scratchpad;

bool flagBufferedNormalized = false;
void bufNormalize(bool enable=true);

int refcount_modules_;
dict<RTLIL::IdString, RTLIL::Module*> modules_;
std::vector<RTLIL::Binding*> bindings_;
Expand Down Expand Up @@ -1210,6 +1213,9 @@ struct RTLIL::Module : public RTLIL::AttrObject
std::vector<RTLIL::IdString> ports;
void fixup_ports();

pool<pair<RTLIL::Cell*, RTLIL::IdString>> bufNormQueue;
void bufNormalize();

template<typename T> void rewrite_sigspecs(T &functor);
template<typename T> void rewrite_sigspecs2(T &functor);
void cloneInto(RTLIL::Module *new_mod) const;
Expand Down Expand Up @@ -1525,6 +1531,9 @@ struct RTLIL::Wire : public RTLIL::AttrObject
int width, start_offset, port_id;
bool port_input, port_output, upto, is_signed;

RTLIL::Cell *driverCell = nullptr;
RTLIL::IdString driverPort;

#ifdef WITH_PYTHON
static std::map<unsigned int, RTLIL::Wire*> *get_all_wires(void);
#endif
Expand Down
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