Generate Graphviz representation without long runtime of 'hierarchy' command #4023
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(Cross-posting from Stack Overflow due to lack of response there; seeking help from the community here) I am using yosys to read a gate-level Verilog file, and subsequently output the design to a Graphviz dot file to visualize it. Measuring the time taken for the yosys commands used, it seems like parsing to an AST is much faster than generating the hierarchy. For example, using a small 9.3MB Verilog design file,
For a larger, real-world design that I tried, the 'hierarchy' command does not end even after about 2 hours. Question: Is it possible to output a Graphviz representation without running the 'hierarchy' command? I tried exploring the options of 'read_verilog' and 'hierarchy' to exclude unneeded operations, but cannot seem to find one that speeds up or omits the 'hierarchy' command. Here is my Tcl script:
Executed with: Output:
If this is not an intended use-case, please let me know as well. |
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Replies: 2 comments 2 replies
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So, the It is possible to omit hierarchy if you are fully aware of the limitations. The main limitation is that it is not in general possible to build the internal representation (netlist) of a verilog module until you know the value of all its parameters, due to things like ports with generic widths, or generate loops that create a different number of copies of some logic. So the main job of The other problem that you could run into with this is that |
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Thank you for your detailed and helpful explanation. As you suggested, I ran Output:
Comparing the different Tcl script runtimes,
Follow-on question: Are there ways to "aggregate" or "simplify" netlists in the parsing commands, for example, skip or group instances of the same type so that not every single one of them is stored into the internal representation (and subsequently into the Graphviz representation)? Besides reducing runtime to parse large circuits, analytical complexity can be reduced as well. Tcl script:
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I think trying to deduplicate the internal representation would take even more computation time, when you are trying to reduce it (though it could possibly reduce memory usage). There's nothing more you can do here if you want to use yosys (theoretically you could try to optimize the frontend but I really do not recommend that, the code is very difficult to touch). If you don't need the yosys feature set but just a graph, you can try and see if any of the other open source verilog frontends can do it faster.