Given an RTLIL::Wire which is assigned to "piecewise", is it possible to find all of the pieces?

[gussmith23]

As a very simple example:

module top(output [1:0] out, input a,b);
  assign out[0] = a;
  assign out[1] = b;
endmodule

If I have the Wire object representing out, is there an easy way to discover that it is defined in pieces, where the first piece is a and the second is b? I thought sigmap might do this, but seems like sigmapping out just gives back out. I also thought chunks might give this info, but it doesn't.

[gussmith23]

Ah, nevermind, answered my own question -- it seems like I can't do sigmap directly on the wire itself, but if I first convert the wire to a SigSpec, then sigmap does what I expected it to do.