naming rule for the synthesised verilog

[nlwmode]

The “\” character that appears in the output verilog file:
Inputs(aig + genlib):

aig 15 7 0 6 8
27
0
1
26
28
30
�	�����
��������i0 G0_pad
i1 G1_pad
i2 G2_pad
i3 G3_pad
i4 G5_reg/NET0131
i5 G6_reg/NET0131
i6 G7_reg/NET0131
o0 G17_pad
o1 _al_n0
o2 _al_n1
o3 g17/_1_
o4 g70/_1_
o5 g74/_0_
c
s27_comb

GATE   zero   0  O=CONST0;
GATE   one    0  O=CONST1;
GATE   buf    2  O=a;              PIN * NONINV 1 999 1.0 0.0 1.0 0.0
GATE   not    1  O=!a;             PIN * INV 1 999 0.9 0.3 0.9 0.3
GATE   nand   2  O=!(a*b);         PIN * INV 1 999 1.0 0.2 1.0 0.2
GATE   nor    2  O=!(a+b);         PIN * INV 1 999 1.4 0.5 1.4 0.5
GATE   and    3  O=a*b;            PIN * NONINV 1 999 1.9 0.3 1.9 0.3
GATE   or     3  O=a+b;            PIN * NONINV 1 999 2.4 0.3 2.4 0.3
GATE   xor    5  O=a*!b+!a*b;      PIN * UNKNOWN 2 999 1.9 0.5 1.9 0.5
GATE   xnor   5  O=a*b+!a*!b;      PIN * UNKNOWN 2 999 2.1 0.5 2.1 0.5

The scripts are:

read_aiger s27_comb.aig

aigmap

techmap

abc -genlib test.genlib

write_verilog test_s27_comb_syn.v

Then, the final synthesised verilog are:

/* Generated by Yosys 0.41+108 (git sha1 e3c09f272, g++ 10.5.0-1ubuntu1~20.04 -fPIC -Os) */

module \/workspace/data/comb/s27_comb.aig (G1_pad, G2_pad, G3_pad, \G5_reg/NET0131 , \G6_reg/NET0131 , \G7_reg/NET0131 , G17_pad, _al_n0, _al_n1, \g17/_1_ , \g70/_1_ , \g74/_0_ , G0_pad);
  wire _00_;
  wire _01_;
  wire _02_;
  wire _03_;
  wire _04_;
  wire _05_;
  wire _06_;
  wire _07_;
  wire _08_;
  wire _09_;
  wire _10_;
  wire _11_;
  wire _12_;
  wire _13_;
  wire _14_;
  wire _15_;
  wire _16_;
  wire _17_;
  wire _18_;
  wire _19_;
  wire _20_;
  wire _21_;
  wire _22_;
  wire _23_;
  wire _24_;
  wire _25_;
  wire _26_;
  wire _27_;
  wire _28_;
  wire _29_;
  wire _30_;
  wire _31_;
  wire _32_;
  input G0_pad;
  wire G0_pad;
  output G17_pad;
  wire G17_pad;
  input G1_pad;
  wire G1_pad;
  input G2_pad;
  wire G2_pad;
  input G3_pad;
  wire G3_pad;
  input \G5_reg/NET0131 ;
  wire \G5_reg/NET0131 ;
  input \G6_reg/NET0131 ;
  wire \G6_reg/NET0131 ;
  input \G7_reg/NET0131 ;
  wire \G7_reg/NET0131 ;
  output _al_n0;
  wire _al_n0;
  output _al_n1;
  wire _al_n1;
  output \g17/_1_ ;
  wire \g17/_1_ ;
  output \g70/_1_ ;
  wire \g70/_1_ ;
  output \g74/_0_ ;
  wire \g74/_0_ ;
  \not  _33_ (
    .O(_12_),
    .a(_00_)
  );
  \not  _34_ (
    .O(_13_),
    .a(_05_)
  );
  \nand  _35_ (
    .O(_14_),
    .a(_12_),
    .b(_06_)
  );
  \nor  _36_ (
    .O(_15_),
    .a(_02_),
    .b(_07_)
  );
  \nand  _37_ (
    .O(_16_),
    .a(_04_),
    .b(_15_)
  );
  \nand  _38_ (
    .O(_17_),
    .a(_14_),
    .b(_16_)
  );
  \nand  _39_ (
    .O(_01_),
    .a(_13_),
    .b(_17_)
  );
  \not  _40_ (
    .O(_09_),
    .a(_01_)
  );
  \and  _41_ (
    .O(_10_),
    .a(_00_),
    .b(_01_)
  );
  \nor  _42_ (
    .O(_11_),
    .a(_03_),
    .b(_15_)
  );
  one _43_ (
    .O(_08_)
  );
  assign _al_n0 = 1'h0;
  assign \g17/_1_  = _09_;
  assign G17_pad = _01_;
  assign _00_ = G0_pad;
  assign \g70/_1_  = _10_;
  assign \g74/_0_  = _11_;
  assign _06_ = \G6_reg/NET0131 ;
  assign _al_n1 = _08_;
  assign _02_ = G1_pad;
  assign _03_ = G2_pad;
  assign _04_ = G3_pad;
  assign _05_ = \G5_reg/NET0131 ;
  assign _07_ = \G7_reg/NET0131 ;
endmodule

The Question

• when do the "\" characters appear?
• why the constant one is also mapped, other than using 1'h0 directly?

[whitequark]

• when do the "" characters appear?

The Verilog specification normally restricts the characters that can appear in identifiers to be alphanumeric, starting with an alphabetic one. The initial backslash expands this character set to include any non-space character, with space being the terminal delimiter.

why the constant one is also mapped, other than using 1'h0 directly?

This is a property of a particular synthesis workflow. Some components of some toolchains require all ports to be connected to wires, otherwise they cannot process the netlist, which is one reason why you might see a wire being driven with a constant. Other reasons you may see this could be convenience of emitting a netlist, or a desire to give the constant a name for debugging purposes. The exact answer will depend on your particular toolchain.

(Note that the single backtick only works for highlighting/escaping code within a single line of Markdown. To add a codeblock you need the triple backtick on its own line before and after.)

[nlwmode]

Thanks for your reply. It well answers my question.