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Yosys 0.46
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@mmicko mmicko released this 09 Oct 06:14
· 270 commits to main since this release
0.46
e97731b

Yosys 0.45 .. Yosys 0.46

  • Various

    • Added new "functional backend" infrastructure with three example
      backends (C++, SMTLIB and Rosette).
    • Added new coarse-grain buffer cell type "$buf" to RTLIL.
    • Added "-y" command line option to execute a Python script with
      libyosys available as a built-in module.
    • Added support for casting to type in Verilog frontend.

  • New commands and options

    • Added "clockgate" pass for automatic clock gating cell insertion.
    • Added "bufnorm" experimental pass to convert design into
      buffered-normalized form.
    • Added experimental "aiger2" and "xaiger2" backends, and an
      experimental "abc_new" command
    • Added "-force-detailed-loop-check" option to "check" pass.
    • Added "-unit_delay" option to "read_liberty" pass.

  • Verific support

    • Added left and right bound properties to wires when using
      specific VHDL types.
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