Now use latest VTR as a submodule

[tangxifan]

Motivate of the pull request

• To address an existing issue. If so, please provide a link to the issue:
• Breaking new feature. If so, please describe details in the description part.

Describe the technical details

What is currently done? (Provide issue link if applicable)

What does this pull request change?

This PR improves in the following aspects:

• Now Verilog-to-Routing is a submodule under the root, being similar to yosys and yosys-plugin.
  • We use a feature branch openfpga under the Verilog-to-Routing official repository. https://github.com/verilog-to-routing/vtr-verilog-to-routing/tree/openfpga. We will merge this feature branch to the master branch of VTR, which may take a few months to complete.
  • Custom version/fork of VPR, abc, ace etc. are removed. All of them come from VTR upstream.
• Adapt OpenFPGA code to use the latest API/data structures from VTR upstream
• Now libopenfpga is renamed to libs
• Provide a python script to upgrade current VPR architecture to the latest (see some XML syntax changes)
  • Use the python script openfpga_flow/scripts/arch_file_updater.py to update VPR architecture
• Ensure no backward compatibility. Golden netlists outputted by FPGA-Verilog should remain the same.
• Ensure all the existing regression tests pass
• Consider to add gcc-10, gcc-11 build compatibility (deployed to CI)
• Remove the support on gcc-5 and gcc-6 due to that VTR only supports gcc-7, 8, 9, 10, 11, clang-6, clang-7, clang-10
• Consider to add no-warning compilation (deployed to CI)
• Consider to add debug compilation (deployed to CI)
• The SDC writer should consider the sorted incoming edges for connection blocks in gsb

Which part of the code base require a change

• VPR
• Tileable routing architecture generator
• OpenFPGA libraries
• FPGA-Verilog
• FPGA-Bitstream
• FPGA-SDC
• FPGA-SPICE
• Flow scripts
• Architecture library
• Cell library
• Documentation
• Regression tests
• Continous Integration (CI) scripts

Impact of the pull request

• Require a change on Quality of Results (QoR)
• Break back-compatibility. If so, please list who may be influenced.

• No changes seen in golden netlists; Expect backward compatibility maintained
• Remove the support on gcc-5 and gcc-6 due to that VTR only supports gcc-7, 8, 9, 10, 11, clang-6, clang-7, clang-10
• Now the most supported OS will be ubuntu 20.04, rather than ubuntu 18.04

[tangxifan]

Critical User interface changes

• Now link_openfpga_arch has a new option ----sort_gsb_ipin_node_in_edges, which can sort the incoming edges for all the ipin nodes of GSBs
• Now link_openfpga_arch has a new option ----sort_gsb_in_edgess, which is a shortcut to run the --sort_gsb_chan_node_in_edges and --sort_gsb_ipin_node_in_edges
• Suggest to call VPR with the option --skip_sync_clustering_and_routing_results off because OpenFPGA has a better sync-up function (supporting more versatile architectures)

Critical QoR Change logs

• Relax the fixed routing channel width from 50 to 60 for the testcase benchmark_sweep/counter128
• Forced a fixed routing channel width of 80 for quicklogic flow tests

[tangxifan]

TODO

• The SDC writer should consider the sorted incoming edges for connection blocks in gsb
• Now link_openfpga_arch has a new option --sort_gsb_ipin_node_in_edges, which can sort the incoming edges for all the ipin nodes of GSBs
• Now link_openfpga_arch has a new option --sort_gsb_in_edges, which is a shortcut to run the --sort_gsb_chan_node_in_edges and --sort_gsb_ipin_node_in_edges
• Consider to add no-warning compilation (deployed to CI)
• Consider to add debug compilation (deployed to CI)
• Apply code formatting