v0.20.0

Release notes

• Use PowSyBl Core 4.8.0 (#480, #509, #518)
• Implements specific parameters from Map (#490)
• AC security analysis cancellation (#491)
• Get original IIDM ID (#494)
• Remove Hvdc Ac emulation OpenLoadFlow parameter (#498)
• Switch contingency support (#501)
• Clean security analysis logs (#519)
• Refactor
  • Clarify buses and branches stored in LfContingency (#504)
  • AC sensitivity analysis: refactoring (#510)
• Various fixes:
  • Fix transformer voltage control with multiple components (#487)
  • Fix: support of non impedant dangling lines (#489)
  • Fix multi components DC LF (#492)
  • Fix security analysis behaviour when network is invalid (#495)
  • Fix HVDC set point increase sensitivity convention (#488)
  • Fix contingency generator for AC computations (#500)
  • Catch MatrixException instead of Exception (#497)
  • DC sensitivity analysis: fix if contingency element is in GLSK (#496)
  • Bug fix: fix network reset (#507)
  • Bug: AC sensitivity analysis with a phase shifter active power control on (#502)
  • Fix DC voltage init (#513)
  • Determinist branchesToOpen order (#516)
  • Fix decremental connectivity (#517)