gz_8p8i waveform

In this core, the inputs work like they do in ordinary IO cores, but the 'pwms' output bus switches each bit dynamically between logic '1' and logic '0' as an internal counter passes the value of a cached value for each pwm output bit. When the internal counter rolls over, the output bits are set back to logic '1' and the cycle repeats. To control the PWM outputs, write a pwm number (0 - 7) to the SPI bus followed by a duty cycle value (0 - 32).

If you look at the upper three signals in the waveform display you will see where the testbench (i.e. the CPU when running in circuit) is stimulating the core. Note that the stimulation ends about halfway across, and that the core activity continues modulating the pulsed output. To support this, the core needs its own clock. In the Guzunty Pi, we use one of the GPIO special out functions (GPCLK0 on GPIO4). The Pi hardware clock output is wired to the 'clk' signal seen in this waveform. It is switching too fast to see the clock as anything other than a stippled band at the resolution of this image. The resource usage in the fitter report reveals a point worthy of discussion. The resource usage for this core is extremely high (Macrocells 96%, Registers 83%). Why? The reason is that this design needs to cache a lot of data, 40 bits just for the individual pwm duty cycle registers. CPLD's don't make great RAM chips. There is only one bit of set/reset storage per Macrocell, we need 40 bits and there are only 72 macrocells in the whole device (and we still need registers for other purposes such as the internal counter).