-
Notifications
You must be signed in to change notification settings - Fork 227
ARM A57
Thomas Roehl edited this page Sep 10, 2018
·
1 revision
The input file for the events on ARM® A57 (ARMv8) can be found here.
The ARM® A57 (ARMv8) microarchitecture provides 6 general-purpose counters consisting of a config and a counter register.
| Counter name | Event name |
|---|---|
| PMC0 | * |
| PMC1 | * |
| PMC2 | * |
| PMC3 | * |
| PMC4 | * |
| PMC5 | * |
Currently no options are available for ARM® A57 (ARMv8). All handling is managed by perf_event.
-
Applications
-
Config files
-
Daemons
-
Architectures
- Available counter options
- AMD
- Intel
- Intel Atom
- Intel Pentium M
- Intel Core2
- Intel Nehalem
- Intel NehalemEX
- Intel Westmere
- Intel WestmereEX
- Intel Xeon Phi (KNC)
- Intel Silvermont & Airmont
- Intel Goldmont
- Intel SandyBridge
- Intel SandyBridge EP/EN
- Intel IvyBridge
- Intel IvyBridge EP/EN/EX
- Intel Haswell
- Intel Haswell EP/EN/EX
- Intel Broadwell
- Intel Broadwell D
- Intel Broadwell EP
- Intel Skylake
- Intel Coffeelake
- Intel Kabylake
- Intel Xeon Phi (KNL)
- Intel Skylake X
- Intel Cascadelake SP/AP
- Intel Tigerlake
- Intel Icelake
- Intel Icelake X
- Intel SappireRapids
- ARM
- POWER
-
Tutorials
-
Miscellaneous
-
Contributing