Skip to content

BroadwellD

Jump to bottom
Thomas Gruber edited this page Mar 2, 2023 · 11 revisions

Architecture specific notes for Intel® Broadwell D

Performance groups

Intel® Broadwell D Performance groups

Events

The input file for the events on Intel® Broadwell D can be found here.

Counters

Core-local counters

Fixed-purpose counters

Since the Core2 microarchitecture, Intel® provides a set of fixed-purpose counters. Each can measure only one specific event.

Counters
Counter name Event name
FIXC0 INSTR_RETIRED_ANY
FIXC1 CPU_CLK_UNHALTED_CORE
FIXC2 CPU_CLK_UNHALTED_REF
Available Options
Option Argument Description Comment
anythread N Set bit 2+(index*4) in config register
kernel N Set bit (index*4) in config register

General-purpose counters

The Intel® Broadwell D microarchitecture provides 4 general-purpose counters consisting of a config and a counter register.

Counters
Counter name Event name
PMC0 *
PMC1 *
PMC2 *
PMC3 *
PMC4 * (only available without HyperThreading)
PMC5 * (only available without HyperThreading)
PMC6 * (only available without HyperThreading)
PMC7 * (only available without HyperThreading)

WARNING: Counters PMC4-7 can only be measured if the 'kernel' option is set. LIKWID does that automatically for these counters. Be aware that the registers are incremented in user- as well as in kernel-space and thus probably have much higher counts. For comparisons with on event in PMC0-3 it is recommended to add the 'kernel' option there as well. (src: Intel® Xeon® E7-8800/4800 v4 Processor Product Family Spec Update)

Available Options
Option Argument Description Comment
edgedetect N Set bit 18 in config register
kernel N Set bit 17 in config register
anythread N Set bit 21 in config register
threshold 8 bit hex value Set bits 24-31 in config register
invert N Set bit 23 in config register
in_transaction N Set bit 32 in config register Only available if Intel® Transactional Synchronization Extensions are available
in_transaction_aborted N Set bit 33 in config register Only counter PMC2 and only if Intel® Transactional Synchronization Extensions are available
Special handling for events

The Intel® Broadwell D microarchitecture provides measureing of offcore events in PMC counters. Therefore the stream of offcore events must be filtered using the OFFCORE_RESPONSE registers. The Intel® Broadwell microarchitecture has two of those registers. LIKWID defines some events that perform the filtering according to the event name. Although there are many bitmasks possible, LIKWID natively provides only the ones with response type ANY. Own filtering can be applied with the OFFCORE_RESPONSE_0_OPTIONS and OFFCORE_RESPONSE_1_OPTIONS events. Only for those events two more counter options are available:

Option Argument Description Comment
match0 16 bit hex value Input value masked with 0x8FFF and written to bits 0-15 in the OFFCORE_RESPONSE register Check the Intel® Software Developer System Programming Manual, Vol. 3, Chapter Performance Monitoring and https://download.01.org/perfmon/BDW-DE.
match1 22 bit hex value Input value is written to bits 16-37 in the OFFCORE_RESPONSE register Check the Intel® Software Developer System Programming Manual, Vol. 3, Chapter Performance Monitoring and https://download.01.org/perfmon/BDW-DE.
The event MEM_TRANS_RETIRED_LOAD_LATENCY is not available because it needs programming of PEBS registers. PEBS is a kernel-level measurement facility for performance monitoring. Although we can program it from user-space, the results are always 0.

Thermal counter

The Intel® Broadwell D microarchitecture provides one register for the current core temperature.

Counters
Counter name Event name
TMP0 TEMP_CORE

Socket-wide counters

Energy counters

The Intel® Broadwell D microarchitecture provides measurements of the current energy consumption through the RAPL interface.

Counters
Counter name Event name
PWR0 PWR_PKG_ENERGY
PWR1 PWR_PP0_ENERGY
PWR2 PWR_PP1_ENERGY
PWR3 PWR_DRAM_ENERGY

Home Agent counters

The Intel® Broadwell D microarchitecture provides measurements of the Home Agent (HA) in the uncore. The description from Intel®:
Each HA is responsible for the protocol side of memory interactions, including coherent and non-coherent home agent protocols (as defined in the Intel® QuickPath Interconnect Specification). Additionally, the HA is responsible for ordering memory reads/writes, coming in from the modular Ring, to a given address such that the IMC (memory controller).
The Home Agent performance counters are exposed to the operating system through PCI interfaces. There are two of those interfaces for the HA. The name BBOX originates from the Nehalem EX uncore monitoring.

Counters
Counter name Event name
BBOX<0,1>C0 *
BBOX<0,1>C1 *
BBOX<0,1>C2 *
BBOX<0,1>C3 *
Available Options
Option Argument Description Comment
edgedetect N Set bit 18 in config register
threshold 8 bit hex value Set bits 24-31 in config register
invert N Set bit 23 in config register

Last Level cache counters

The Intel® Broadwell D microarchitecture provides measurements of the LLC coherency engine in the uncore. The description from Intel®:
The LLC coherence engine (CBo) manages the interface between the core and the last level cache (LLC). All core transactions that access the LLC are directed from the core to a CBo via the ring interconnect. The CBo is responsible for managing data delivery from the LLC to the requesting core. It is also responsible for maintaining coherence between the cores within the socket that share the LLC; generating snoops and collecting snoop responses from the local cores when the MESIF protocol requires it.
The LLC hardware performance counters are exposed to the operating system through the MSR interface. The maximal amount of supported coherency engines for the Intel® Broadwell D microarchitecture is 16. It may be possible that your systems does not have all CBOXes, LIKWID will skip the unavailable ones in the setup phase. The name CBOX originates from the Nehalem EX uncore monitoring.

Counters
Counter name Event name
CBOX<0-15>C0 *
CBOX<0-15>C1 *
CBOX<0-15>C2 *
CBOX<0-15>C3 *
Available Options
Option Argument Operation Comment
edgedetect N Set bit 18 in config register
threshold 8 bit hex value Set bits 24-31 in config register
tid 6 bit hex value Set bits 0-5 in MSR_UNC_V3_C<0-15>_PMON_BOX_FILTER0 register
state 7 bit hex value Set bits 17-23 in MSR_UNC_V3_C<0-15>_PMON_BOX_FILTER0 register M': 0x40
,D: 0x20,
F: 0x10,
M: 0x08,
E: 0x04,
S: 0x02,
I: 0x01
nid 16 bit hex value Set bits 0-15 in MSR_UNC_V3_C<0-15>_PMON_BOX_FILTER1 register Note: Node 0 has value 0x0001
opcode 9 bit hex value Set bits 20-28 in MSR_UNC_V3_C<0-15>_PMON_BOX_FILTER1 register A list of valid opcodes can be found in the Intel® Xeon D-1500 uncore Manual.
match0 2 bit hex address Set bits 30-31 in MSR_UNC_V3_C<0-15>_PMON_BOX_FILTER1 register See the Intel® Xeon D-1500 uncore Manual for more information.
Special handling for events

The Intel® Broadwell D microarchitecture provides an event LLC_LOOKUP which can be filtered with the 'state' option. If no 'state' is set, LIKWID sets the state to 0x1F, the default value to measure all lookups.

Uncore management fixed-purpose counter

The Intel® Broadwell D microarchitecture provides measurements of the management box in the uncore. The description from Intel®:
The UBox serves as the system configuration controller for the Intel® Xeon® Processor D-1500 Product Family.
In this capacity, the UBox acts as the central unit for a variety of functions:

  • The master for reading and writing physically distributed registers across Intel® Xeon processor E5 v3 family using the Message Channel.
  • The UBox is the intermediary for interrupt traffic, receiving interrupts from the system and dispatching interrupts to the appropriate core.
  • The UBox serves as the system lock master used when quiescing the platform (e.g., Intel® QPI bus lock).

The single fixed-purpose counter counts the clock frequency of the clock source of the uncore. The uncore management performance counters are exposed to the operating system through the MSR interface. The name UBOX originates from the Nehalem EX uncore monitoring.

Counter
Counter name Event name
UBOXFIX UNCORE_CLOCK

Uncore management general-purpose counters

The Intel® Broadwell D microarchitecture provides measurements of the management box in the uncore. The description from Intel®:
The UBox serves as the system configuration controller for the Intel® Xeon® Processor D-1500 Product Family.
In this capacity, the UBox acts as the central unit for a variety of functions:

  • The master for reading and writing physically distributed registers across Intel® Xeon processor E5 v3 family using the Message Channel.
  • The UBox is the intermediary for interrupt traffic, receiving interrupts from the system and dispatching interrupts to the appropriate core.
  • The UBox serves as the system lock master used when quiescing the platform (e.g., Intel® QPI bus lock).

The uncore management performance counters are exposed to the operating system through the MSR interface. The name UBOX originates from the Nehalem EX uncore monitoring.

Counter
Counter name Event name
UBOX0 *
UBOX1 *
Available Options
Option Argument Operation Comment
edgedetect N Set bit 18 in config register
threshold 5 bit hex value Set bits 24-28 in config register
invert N Set bit 23 in config register

Power control unit fixed-purpose counters

The Intel® Broadwell D microarchitecture provides measurements of the power control unit (PCU) in the uncore. The description from Intel®:
The PCU is the primary Power Controller for the Intel® Xeon® Processor D-1500 Product Family. The uncore implements a power control unit acting as a core/uncore power and thermal manager. It runs its firmware on an internal micro-controller and coordinates the socket’s power states.

The PCU offers two fixed-purpose counters to retrieve the cycles CPU cores stay in state C6 and C3. The uncore management performance counters are exposed to the operating system through the MSR interface. The name WBOX originates from the Nehalem EX uncore monitoring.

Counters
Counter name Event name
WBOX0FIX CORES_IN_C3
WBOX1FIX CORES_IN_C6

Power control unit general-purpose counters

The Intel® Broadwell D microarchitecture provides measurements of the power control unit (PCU) in the uncore. The description from Intel®:
The PCU is the primary Power Controller for the Intel® Xeon® Processor D-1500 Product Family. The uncore implements a power control unit acting as a core/uncore power and thermal manager. It runs its firmware on an internal micro-controller and coordinates the socket’s power states.

The PCU performance counters are exposed to the operating system through the MSR interface. The name WBOX originates from the Nehalem EX uncore monitoring.

Counters
Counter name Event name
WBOX0 *
WBOX1 *
WBOX2 *
WBOX3 *
Available Options
Option Argument Operation Comment
edgedetect N Set bit 18 in config register
threshold 5 bit hex value Set bits 24-28 in config register
match0 32 bit hex value Set bits 0-31 in
MSR_UNC_V3_PCU_PMON_BOX_FILTER register		 Band0: bits 0-7,
Band1: bits 8-15,
Band2: bits 16-23,
Band3: bits 24-31
occupancy 2 bit hex value Set bit 14-15 in config register Cores
in C0: 0x1,
in C3: 0x2,
in C6: 0x3
occ_edgedetect N Set bit 31 in config register
occ_invert N Set bit 30 in config register

Memory controller fixed-purpose counters

The Intel® Broadwell D microarchitecture provides measurements of the integrated Memory Controllers (iMC) in the uncore. The description from Intel®:
The Intel® Xeon® Processor D-1500 Product Family integrated Memory Controller provides the interface to DRAM and communicates to the rest of the Uncore through the Home Agent (i.e. the IMC does not connect to the Ring).
In conjunction with the HA, the memory controller also provides a variety of RAS features.

The integrated Memory Controllers performance counters are exposed to the operating system through PCI interfaces. There may be two memory controllers in the system. There are four different PCI devices per memory controller, each covering one memory channel. Each channel has one fixed counter for the DRAM clock. The four channels of the first memory controller are MBOX0-3, the four channels of the second memory controller (if available) are named MBOX4-7. The name MBOX originates from the Nehalem EX uncore monitoring.

Counters
Counter name Event name
MBOX<0-7>FIX DRAM_CLOCKTICKS
##### Available Options
Option Argument Operation Comment
invert N Set bit 23 in config register

Memory controller general-purpose counters

The Intel® Broadwell D microarchitecture provides measurements of the integrated Memory Controllers (iMC) in the uncore. The description from Intel®:
The Intel® Xeon® Processor D-1500 Product Family integrated Memory Controller provides the interface to DRAM and communicates to the rest of the Uncore through the Home Agent (i.e. the IMC does not connect to the Ring).
In conjunction with the HA, the memory controller also provides a variety of RAS features.

The integrated Memory Controllers performance counters are exposed to the operating system through PCI interfaces. There may be two memory controllers in the system. There are four different PCI devices per memory controller, each covering one memory channel. Each channel has one fixed counter for the DRAM clock. The four channels of the first memory controller are MBOX0-3, the four channels of the second memory controller (if available) are named MBOX4-7. The name MBOX originates from the Nehalem EX uncore monitoring.

Counters
Counter name Event name
MBOX<0-7>C0 *
MBOX<0-7>C1 *
MBOX<0-7>C2 *
MBOX<0-7>C3 *
Available Options
Option Argument Operation Comment
edgedetect N Set bit 18 in config register
threshold 8 bit hex value Set bits 24-31 in config register
invert N Set bit 23 in config register

Ring-to-PCIe counters

The Intel® Broadwell D microarchitecture provides measurements of the Ring-to-PCIe (R2PCIe) interface in the uncore. The description from Intel®:
R2PCIe represents the interface between the Ring and IIO traffic to/from PCIe.

The Ring-to-PCIe performance counters are exposed to the operating system through a PCI interface. Independent of the system's configuration, there is only one Ring-to-PCIe interface per CPU socket.

Counters
Counter name Event name
PBOX0 *
PBOX1 *
PBOX2 *
PBOX3 *
Available Options
Option Argument Operation Comment
edgedetect N Set bit 18 in config register
threshold 8 bit hex value Set bits 24-31 in config register
invert N Set bit 23 in config register

IRP box counters

The Intel® Broadwell D microarchitecture provides measurements of the IRP box in the uncore. The description from Intel®:
IRP is responsible for maintaining coherency for IIO traffic that needs to be coherent (e.g. cross-socket P2P).

The IRP box counters are exposed to the operating system through the PCI interface. The IBOX was introduced with the Intel® IvyBridge EP/EN/EX microarchitecture.

Counters
Counter name Event name
IBOX<0,1>C0 *
IBOX<0,1>C1 *
Available Options
Option Argument Operation Comment
edgedetect N Set bit 18 in config register
threshold 8 bit hex value Set bits 24-31 in config register
invert N Set bit 23 in config register
Clone this wiki locally