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ARM NEON N1
Thomas Roehl edited this page Nov 16, 2020
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The only known implementation of this architecture is currently AWS Graviton 2.
ARM Neoverse N1 Performance groups
The input file for the events on ARM Neoverse N1 (ARMv8) can be found here.
The ARM Neoverse N1 (ARMv8) microarchitecture provides 6 general-purpose counters consisting of a config and a counter register.
| Counter name | Event name |
|---|---|
| PMC0 | * |
| PMC1 | * |
| PMC2 | * |
| PMC3 | * |
| PMC4 | * |
| PMC5 | * |
Currently no options are available for ARM Neoverse N1 (ARMv8). All handling is managed by perf_event.
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Applications
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Config files
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Daemons
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Architectures
- Available counter options
- AMD
- Intel
- Intel Atom
- Intel Pentium M
- Intel Core2
- Intel Nehalem
- Intel NehalemEX
- Intel Westmere
- Intel WestmereEX
- Intel Xeon Phi (KNC)
- Intel Silvermont & Airmont
- Intel Goldmont
- Intel SandyBridge
- Intel SandyBridge EP/EN
- Intel IvyBridge
- Intel IvyBridge EP/EN/EX
- Intel Haswell
- Intel Haswell EP/EN/EX
- Intel Broadwell
- Intel Broadwell D
- Intel Broadwell EP
- Intel Skylake
- Intel Coffeelake
- Intel Kabylake
- Intel Xeon Phi (KNL)
- Intel Skylake X
- Intel Cascadelake SP/AP
- Intel Tigerlake
- Intel Icelake
- Intel Icelake X
- Intel SappireRapids
- Intel GraniteRapids
- Intel SierraForrest
- ARM
- POWER
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Tutorials
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Miscellaneous
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Contributing