0.8.2a1

What's Changed

• adding little helper tool like icepll by @multigcs in #178
• Add support for the GW2A series by @yrabbit in #181
• Increase verbosity when uploading to PyPi by @yrabbit in #182
• use compressed pickle files by @pepijndevos in #183

New Contributors

• @multigcs made their first contribution in #178

Full Changelog: 0.8.1...0.8.2a1

0.8.1

What's Changed

• Explain how to compile for Tangnano9k by @yrabbit in #173
• BUGFIX: DFF and DFFN reset state by @yrabbit in #176
• Added new oscillator types and improved its handling by @yrabbit in #174
• Change the IO coding to synthetic by @yrabbit in #177

Full Changelog: 0.8...0.8.1

0.8

What's Changed

• BUGFIX: fix the "default" attribute unpacking by @yrabbit in #166
• Replace DFF fuzzer with table data by @yrabbit in #164
• BUGFIX: assign slightly more meaningful names by @yrabbit in #171
• Add support for OSER primitives by @yrabbit in #170

Full Changelog: 0.7...0.8

0.7

What's Changed

• stage 2: Add support for GW1NR-9 PLL by @yrabbit in #160
• stage 2. Add PLL support for GW1NR-4 chips by @yrabbit in #162
• stage2. Add PLL support for GW1NS-2 chips by @yrabbit in #163

Full Changelog: 0.6.2...0.7

0.6.2

What's Changed

• Don't create GTx aliases along the central column by @yrabbit in #147
• Do not send nextpnr wires of dubious purpose by @yrabbit in #148
• Bring examples into line with the current config by @yrabbit in #149
• Add the alonenode mechanism by @yrabbit in #150
• GW1N-9x: Add two rows as normal clock ones by @yrabbit in #151
• Install yowasp from test pypy by @pepijndevos in #152
• Update yosys and nextpnr release versions we test with by @pepijndevos in #153
• stage 2. Add GW1NSR-4C PLLs by @yrabbit in #154
• stage 2: Add support for GW1NR-9C PLL by @yrabbit in #156

Full Changelog: 0.6.1...0.6.2

0.6.1

What's Changed

• Fix the creation of implicit clock wires by @yrabbit in #144

Full Changelog: 0.6...0.6.1

0.6

What's Changed

• Fix table offsets when reading the dat-file by @yrabbit in #137
• Document the logicinfo table by @yrabbit in #138
• Do clock aliases on the bottom row by @yrabbit in #141
• Add ability to use the clock net for PLL signals by @yrabbit in #139

Full Changelog: 0.5.1...0.6

0.5.1

What's Changed

• Add information about the functions of the pins.o by @yrabbit in #135
• Add parameter check and DUTY handling by @yrabbit in #134

Full Changelog: 0.5...0.5.1

0.5.1a1

What's Changed

• Add information about the functions of the pins.o by @yrabbit in #135

Full Changelog: 0.5...0.5.1a1

0.5

What's Changed

• Corrects a typo in the unpacker. by @yrabbit in #116
• Long wires: bugfix by @yrabbit in #118
• WIP shadow RAM packer by @pepijndevos in #111
• packer: uniform type check by @yrabbit in #119
• packer: generalization of ignored cell types by @yrabbit in #121
• Add a directory with global network router tests by @yrabbit in #114
• don't unpack RAM dff by @pepijndevos in #122
• Redo to autodetect the location of I/O banks by @yrabbit in #128
• Make less dependencies required by @mmicko in #132
• Add initial PLL support by @yrabbit in #133

Full Changelog: 0.4...0.5