0.15

What's Changed

• add magic sdram pin constraints by @pepijndevos in #280
• Implement EMCU primitive by @yrabbit in #279
• Fix mistype. by @yrabbit in #283

Full Changelog: 0.14...0.15

0.14

What's Changed

• Assign missing time delays by @yrabbit in #272
• BUGFIX. Fix dat offset. by @yrabbit in #274
• Remove the magic numbers by @yrabbit in #275
• Use builtin USB-serial by @yrabbit in #276
• Implement the UserFlash primitives. by @yrabbit in #277
• Add DHCEN primitive. by @yrabbit in #261

Full Changelog: 0.13...0.14

0.13

What's Changed

• Add PLL pads. by @yrabbit in #241
• Doc. Brief notes on DSP operation by @yrabbit in #246
• Fix CI by @yrabbit in #248
• BUGFIX. Fix BSRAM unpacking. by @yrabbit in #247
• Add description of BSRAM harness by @yrabbit in #249
• Fix IO unpack by @yrabbit in #250
• Describe the BSRAM regs in GW1NR-9C and GW2AR-18C by @yrabbit in #251
• BSRAM. Corrective action. by @yrabbit in #252
• BSRAM BLKSEL fix by @yrabbit in #254
• Clarification in the doc about BSRAM BLKSEL by @yrabbit in #255
• Relax BSRAM initialization data requirements by @yrabbit in #253
• Fix regex by @max-kudinov in #259
• Fix pROM(X9). by @yrabbit in #256
• Implement power saving primitive BANDGAP by @yrabbit in #257
• Fix bits to bytes conversion. by @yrabbit in #265
• Add wire class info by @yrabbit in #266
• Add dynamic clock control by @yrabbit in #260
• HCLK Support by @Seyviour in #258
• HCLK. Primary clock pins by @yrabbit in #263
• Add delays for primary clocks. by @yrabbit in #270

New Contributors

• @max-kudinov made their first contribution in #259

Full Changelog: 0.12...0.13

0.12

What's Changed

• Add examples with tiny RISCV by @yrabbit in #236
• Add Functions for Concise Tile Parsing by @Seyviour in #237
• update yosys CI branches by @pepijndevos in #238
• Implement the DSP primitive. by @yrabbit in #239

Full Changelog: 0.11.1...0.12

0.11.1

What's Changed

• BUGFIX: Use parsed device. by @yrabbit in #214
• Doc. Mention SZFPGA (GW1NR-9) board as supported. by @yrabbit in #218
• Refactor dat parser by @DavidVentura in #212
• Fix #219: Python3.8 compatiblity by @DavidVentura in #221
• Properly handle external 9C clock pins by @yrabbit in #222
• Switch crcmod to crc by @pepijndevos in #223
• Add an example for OSER10 using ELVDS pins by @yrabbit in #226
• Add support for four IOLOGICs in one cell by @yrabbit in #227
• switch readme to nextpnr-himbaechel by @pepijndevos in #228
• bump yosys and nextpnr versions by @pepijndevos in #229
• Update workflows by @mmicko in #233
• Extend SDRAM Documentation to Cover GW2AR-18 Devices by @Seyviour in #231
• Examples. Describe the Tangnano4k clock pin. by @yrabbit in #234
• Replace numpy arrays with lists. by @yrabbit in #230

New Contributors

• @DavidVentura made their first contribution in #212

Full Changelog: 0.10.0...0.11.1

0.10.0

What's Changed

• A Parser For Vendor Provided .ini Files by @Seyviour in #205
• himbaechel: Add OSER10 TLVDS example. by @yrabbit in #207
• Himbaechel. Add initial BSRAM support by @yrabbit in #202
• Add 20k devices to readme by @pepijndevos in #209

New Contributors

• @Seyviour made their first contribution in #205

Full Changelog: 0.9.1...0.10.0

0.9.1

What's Changed

• Himbaechel. Improve dedicated clock router by @yrabbit in #199

Full Changelog: 0.9.0...0.9.1

0.9.0

What's Changed

• Adapting the packer to the alternative P&R by @yrabbit in #184
• Fix simple examples by @yrabbit in #198
• Modify CI to generate Himbaechel bases, build and test Himbaechel examples by @yrabbit in #197

Full Changelog: 0.8.3...0.9.0

0.9.0a1

What's Changed

• Adapting the packer to the alternative P&R by @yrabbit in #184

Full Changelog: 0.8.3...0.9.0a1

0.8.3

What's Changed

• Install gowin_pll tool by @whitequark in #192
• update stable CI versions by @pepijndevos in #190
• Fix OPEN_DRAIN IO attribute by @yrabbit in #194

Full Changelog: 0.8.2...0.8.3