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rtlil: Adjust internal check for $mem_v2 cells #4723

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Nov 18, 2024
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rtlil: Adjust internal check for $mem_v2 cells #4723

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6 changes: 3 additions & 3 deletions kernel/rtlil.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -397,7 +397,7 @@
}

// signed needs one leading bit
if (is_signed && idx < size()) {

Check warning on line 400 in kernel/rtlil.cc

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comparison of integers of different signs: 'size_t' (aka 'unsigned long') and 'int' [-Wsign-compare]

Check warning on line 400 in kernel/rtlil.cc

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comparison of integer expressions of different signedness: ‘size_t’ {aka ‘long unsigned int’} and ‘int’ [-Wsign-compare]

Check warning on line 400 in kernel/rtlil.cc

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GitHub Actions / test-compile (ubuntu-20.04, clang-10) 

comparison of integers of different signs: 'size_t' (aka 'unsigned long') and 'int' [-Wsign-compare]

Check warning on line 400 in kernel/rtlil.cc

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GitHub Actions / test-compile (ubuntu-latest, clang) 

comparison of integers of different signs: 'size_t' (aka 'unsigned long') and 'int' [-Wsign-compare]

Check warning on line 400 in kernel/rtlil.cc

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GitHub Actions / test-compile (ubuntu-latest, clang) 

comparison of integers of different signs: 'size_t' (aka 'unsigned long') and 'int' [-Wsign-compare]

Check warning on line 400 in kernel/rtlil.cc

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GitHub Actions / test-compile (ubuntu-latest, gcc) 

comparison of integer expressions of different signedness: ‘size_t’ {aka ‘long unsigned int’} and ‘int’ [-Wsign-compare]

Check warning on line 400 in kernel/rtlil.cc

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GitHub Actions / test-compile (ubuntu-latest, gcc) 

comparison of integer expressions of different signedness: ‘size_t’ {aka ‘long unsigned int’} and ‘int’ [-Wsign-compare]

Check warning on line 400 in kernel/rtlil.cc

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GitHub Actions / test-compile (macos-13, clang) 

comparison of integers of different signs: 'size_t' (aka 'unsigned long') and 'int' [-Wsign-compare]

Check warning on line 400 in kernel/rtlil.cc

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GitHub Actions / test-compile (macos-13, clang) 

comparison of integers of different signs: 'size_t' (aka 'unsigned long') and 'int' [-Wsign-compare]
idx++;
}
// must be at least one bit
Expand Down Expand Up @@ -1856,9 +1856,9 @@
param_bits(ID::RD_COLLISION_X_MASK, max(1, param(ID::RD_PORTS) * param(ID::WR_PORTS)));
param_bits(ID::RD_WIDE_CONTINUATION, max(1, param(ID::RD_PORTS)));
param_bits(ID::RD_CE_OVER_SRST, max(1, param(ID::RD_PORTS)));
param_bits(ID::RD_ARST_VALUE, param(ID::RD_PORTS) * param(ID::WIDTH));
param_bits(ID::RD_SRST_VALUE, param(ID::RD_PORTS) * param(ID::WIDTH));
param_bits(ID::RD_INIT_VALUE, param(ID::RD_PORTS) * param(ID::WIDTH));
param_bits(ID::RD_ARST_VALUE, max(1, param(ID::RD_PORTS) * param(ID::WIDTH)));
param_bits(ID::RD_SRST_VALUE, max(1, param(ID::RD_PORTS) * param(ID::WIDTH)));
param_bits(ID::RD_INIT_VALUE, max(1, param(ID::RD_PORTS) * param(ID::WIDTH)));
param_bits(ID::WR_CLK_ENABLE, max(1, param(ID::WR_PORTS)));
param_bits(ID::WR_CLK_POLARITY, max(1, param(ID::WR_PORTS)));
param_bits(ID::WR_WIDE_CONTINUATION, max(1, param(ID::WR_PORTS)));
Expand Down
9 changes: 9 additions & 0 deletions tests/memories/nordports.ys
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Original file line number Diff line number Diff line change
@@ -0,0 +1,9 @@
# check memory_collect doesn't produce invalid RTLIL on a memory w/o read ports
read_rtlil <<EOF
autoidx 1
attribute \top 1
module \top
memory width 4 size 3 \foo
end
EOF
memory_collect
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