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This reverts part of D149033 and rG8f966cedea594d9a91e585e88a80a42c04049e6c. The added test case is kept to avoid future regression. Reviewed By: vzakhari, vdonaldson Differential Revision: https://reviews.llvm.org/D149639
We don't have i1 vector shuffle lowering.
Element-wise log(exp) does no operation so that we can fold it into no-op effectively. Reviewed By: eric-k256 Differential Revision: https://reviews.llvm.org/D149632
Some mid-air collision between a change in the generic format and this new python test.
llvm::CodeGen was missing so add them to deps Reviewed By: csigg Differential Revision: https://reviews.llvm.org/D149720
We previously used a more stricter -nostdlib option which was also removing compiler-rt/libgcc. Reviewed By: jhuber6 Differential Revision: https://reviews.llvm.org/D149683
…tests on Windows" This reverts commit 63f0fdc. Since f1431bb, this environment variable is always set up by lit itself, so individual test suites don't need to set it. Differential Revision: https://reviews.llvm.org/D149356
There was a discrepancy where the flag was honored when passed through the command line, but not when passed through the API, which was leading to a python test failing.
This test was added by the change which removed typed pointer support. We saved typed pointer support that's why this test expectedly fails. Using COM: results in test being UNRESOLVED.
Small split change from D146023. Migrate elf-notes to v4 and fix llvm-readobj to work with PAL metadata. Reviewed By: kzhuravl Differential Revision: https://reviews.llvm.org/D146119
Restore code removed incorrectly in merge.
hlfir.region_assign is a Region based version of hlfir.assign: the right-hand side and left-hand-side are evaluated in their own region, and an optional region can be added to implement user defined assignment. This will be used for: - assignments inside where and forall - user defined assignments - assignments to vector subscripted entities. Rational: Forall and Where lowering requires solving an expression/assignment evaluation scheduling problem based on data dependencies between the variables being assigned and the one used in the expressions. Keeping left-hand side and right-hand side in their own region will make it really easy to analyse the dependency and move around the expression evaluation as a whole. Operation DAGs are hard to scissor out when the LHS and RHS evaluation are lowered in the same block. The pass dealing with further forall/where lowering in HLFIR will need to succeed. It is not acceptable for them to fail splitting the RHS/LHS evaluation code. Keeping them in independent block is an approach that cannot fail. For user defined assignments, having a region allows implementing all the call details in lowering, and even to allow inlining of the user assignment, before it is decided if a temporary for the LHS or RHS is required or not. The operation description mention "hlfir.elemental_addr" (operation that will be used for vector subscripted LHS) and "ordered assignment trees" (concept/inetrface that will be used to represent forall/where structure in HLFIR). These will be pushed in follow-up patch, but I do not want t scissor out the descriptions. Differential Revision: https://reviews.llvm.org/D149442
Pass on address space information to SPIR-V Joint Matrix Load/Store intrinsics. --------- Signed-off-by: Sidorov, Dmitry <dmitry.sidorov@intel.com> Co-authored-by: Sidorov, Dmitry <dmitry.sidorov@intel.com>
* According to the [specification](https://registry.khronos.org/SYCL/specs/sycl-2020/html/sycl-2020.html#sec:accessor.local) a local accessor must not be used in a SYCL kernel function that is invoked via single_task or via the simple form of parallel_for that takes a range parameter. * Modifies existing misuse in tests. * This PR was once reviewed and merged in, but it was reverted as needed AccessTargetMask as an exported symbol on Windows to be added. --------- Co-authored-by: Alexey Bader <alexey.bader@intel.com> Co-authored-by: Mahmoud Moadeli <mahmoudmoadeli@ed-pcsa-4da5.build.codeplay.com> Co-authored-by: Steffen Larsen <steffen.larsen@intel.com>
…ment See the operation description in HLFIROps.td. Depends on D149442 Differential Revision: https://reviews.llvm.org/D149449
Lower vector subscripted designators as values when they appear outside of the assignment left-hand side and input IO contexts. This matches Fortran semantics where vector subscripted designators cannot be written to outside of the two contexts mentioned above: they are passed/taken by value where they appear. This patch uses the added hlfir.element_addr to lower vector designators in lowering. But when reaching the end of the designator lowering, the hlfir.element_addr is turned into an hlfir.elemental when lowering is not asking for the hlfir.elemental_addr. This approach allows lowering vector subscripted in the same way in while visiting the designator, and only adapt to the context at the edge. The part where lowering uses the hlfir.elemental_addr will be done in further patch as it requires lowering assignments in the new hlfir.region_assign op, and there is not codegen yet for these new operations. Differential Revision: https://reviews.llvm.org/D149480
Allow shrink-wrapping past memory accesses that only access globals or function arguments. This patch uses getUnderlyingObject to try to identify the accessed object by a given memory operand. If it is a global or an argument, it does not access the stack of the current function and should not block shrink wrapping. Note that the caller's stack may get accessed when passing an argument via the stack, but not the stack of the current function. This addresses part of the TODO from D63152. Reviewed By: thegameg Differential Revision: https://reviews.llvm.org/D149668
OutputSection::checkDynRelAddends() incorrectly reports an internal linker error for large addends on 32-bit targets. This is caused by the lack of sign extension in DynamicReloc::computeAddend() for 32-bit addends. Differential Revision: https://reviews.llvm.org/D149347
It was rejected in C, and in a strange way accepted in C++. However, the support was never properly tested and fully implemented, so just reject it in C++ mode as well. This change also fixes crash on attempt to initialize union with flexible array member. Due to missing check on union, there was a null expression added to init list that caused crash later. Fixes llvm/llvm-project#61746 Reviewed By: aaron.ballman Differential Revision: https://reviews.llvm.org/D147626
Reviewed By: jpienaar Differential Revision: https://reviews.llvm.org/D149152
This reverts commit 22e2db6. Broke buildbots on Windows. It seems standard headers on Windows contain flexible array members in unions
…ntel#9135) Signed-off-by: Tikhomirova, Kseniya <kseniya.tikhomirova@intel.com>
DG2 doesn't support the sqrtm instruction used in the test. Signed-off-by: Sarnie, Nick <nick.sarnie@intel.com>
This tries to push the concat in trunc(concat(rshr, rshr)) into the leaves, so that we can generate rshrn(concat). This helps improve the codegen for small types, using the existing rshrn patterns. Differential Revision: https://reviews.llvm.org/D149636
The previous pattern was matching the RVA `0` to the first character of `0x1010`. Make sure now that the entire export entry is matched.
…exports ordinals are large.
intel#8848 Signed-off-by: Jaime Arteaga <jaime.a.arteaga.molina@intel.com>
intel#9052 Signed-off-by: Jaime Arteaga <jaime.a.arteaga.molina@intel.com>
intel#8763 Signed-off-by: Jaime Arteaga <jaime.a.arteaga.molina@intel.com>
Signed-off-by: Jaime Arteaga <jaime.a.arteaga.molina@intel.com>
Signed-off-by: Jaime Arteaga <jaime.a.arteaga.molina@intel.com>
https://github.com/intel/llvm/pull/8603/files Signed-off-by: Jaime Arteaga <jaime.a.arteaga.molina@intel.com>
intel#9094 Signed-off-by: Jaime Arteaga <jaime.a.arteaga.molina@intel.com>
Signed-off-by: Jaime Arteaga <jaime.a.arteaga.molina@intel.com>
intel#9109 Signed-off-by: Jaime Arteaga <jaime.a.arteaga.molina@intel.com>
intel#9067 Signed-off-by: Jaime Arteaga <jaime.a.arteaga.molina@intel.com>
Signed-off-by: Jaime Arteaga <jaime.a.arteaga.molina@intel.com>
intel#8982 Signed-off-by: Jaime Arteaga <jaime.a.arteaga.molina@intel.com>
* Fix failing device CTS Signed-off-by: Brandon Yates <brandon.yates@intel.com>
Signed-off-by: Jaime Arteaga <jaime.a.arteaga.molina@intel.com>
Signed-off-by: Jaime Arteaga <jaime.a.arteaga.molina@intel.com>
Signed-off-by: Jaime Arteaga <jaime.a.arteaga.molina@intel.com>
Signed-off-by: Jaime Arteaga <jaime.a.arteaga.molina@intel.com>
intel#9203 Signed-off-by: Jaime Arteaga <jaime.a.arteaga.molina@intel.com>
intel#9243 Signed-off-by: Jaime Arteaga <jaime.a.arteaga.molina@intel.com>
intel#9275 Signed-off-by: Jaime Arteaga <jaime.a.arteaga.molina@intel.com>
Signed-off-by: Jaime Arteaga <jaime.a.arteaga.molina@intel.com>
Signed-off-by: Jaime Arteaga <jaime.a.arteaga.molina@intel.com>
intel#9300 Signed-off-by: Jaime Arteaga <jaime.a.arteaga.molina@intel.com>
* Fixes for porting to UR repo Signed-off-by: Brandon Yates <brandon.yates@intel.com> --------- Signed-off-by: Brandon Yates <brandon.yates@intel.com>
Signed-off-by: Brandon Yates <brandon.yates@intel.com>
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