v3.3.0

API Modification

(#1201) Don't use MuxLookup default for full mapping
(#1315) Emit FIRRTL andr, orr for Bits.{andR, orR}
(#1359) Cleanup aspects
(#1384) No more compile internal

Fix

(#1136) Make Queue.irrevocable work properly in chisel3 - Close #1134
(#1224) Improve naming of anonymous/class-in-function Modules
(#1246) Fix mergify to backports: omit jenkins CI
(#1252) Fix bidirectional Wire with Analog
(#1256) Fix deprecation warning that leaks into user code
(#1258) Fix asTypeOf for Clock
(#1274) Bug fixes to support code for Interval
(#1275) Fixed problem creating Interval literals with full ranges
(#1283) BitPat supports whitespace and underscores
(#1294) Fixed code example typo in comment
(#1303) Bugfix: Select.instances now works with blackboxes
(#1324) fix mill build
(#1336) Fix := of Reset and AsyncReset to DontCare
(#1346) Patch fix #1109
(#1374) Dont wrap elaboration annotations
(#1380) Use innermost builder cause to trim stack trace
(#1387) Propagate user compile options for Chisel.Module
(#1399) Fix mill build

Feature

(#1180) Add brief description of (current) chisel versioning and version recommendations.
(#1183) Add read-under-write parameter to SyncReadMem
(#1209) Enable @chiselName on non-module classes
(#1213) Deprecate Driver methods in favor of ChiselStage
(#1215) Add ChiselEnum to BundleLiterals
(#1225) Support literals cast to aggregates as async reset reg init values
(#1227) Bump master SNAPSHOT version.
(#1236) Add MiMa and CI checks for binary compatibility
(#1237) Remove over design
(#1239) Improve error message when assigning from Seq to Vec
(#1243) Add CCC20 Info at README top
(#1244) Create .mergify.yml
(#1253) Compat compile options macro
(#1260) Update README to reflect CCC20 Extension
(#1264) Remove Jenkins CI from .mergify.yml
(#1268) Revert "Compat compile options macro"
(#1270) Migrate to Dependency Wrapper
(#1273) Remove unused WriteEmitted phase
(#1277) Band aid until litOption is implemented for Aggregates.
(#1284) Provides Double and BigDecimal methods to access literal values for FixedPoint and Interval
(#1285) Add method asBool to Clock.
(#1296) Remove redundancy code
(#1305) specifying type of targets field in ChiselStage
(#1308) Change when/switch thunk type to Any
(#1309) Big decimal methods for num types.2
(#1318) Add Scaladoc about RegNext Unset/Inferred Widths
(#1325) README: have a link to the classic tutorial
(#1326) Printf: Add support for tabs, and give helpful error messages (#1323)
(#1329) Clone child elements lazily in Vec
(#1332) Bump sbt and tool/plugin dependencies.
(#1340) Update sbt-site to 1.3.3
(#1341) Update junit to 4.13
(#1342) Update paradise to 2.1.1
(#1345) Upcoming Events: Remove CCC, add Dev Meetings
(#1356) sbt compatible publish for mill
(#1357) add testOnly
(#1360) Make implicit clock and reset final vals
(#1361) Provide API to set concrete type of implicit reset
(#1365) Retain default version assignment
(#1367) Java API Documents Linking
(#1372) Make mergify open backport PRs & signal on failed cherry-picks
(#1373) [mergify] Update match string for labeling backported PRs
(#1377) Remove toNamed (and friends) deprecation.
(#1382) Set StageError cause in ChiselStage
(#1383) Add NoChiselNamePrefix to ignore instances in @chiselName
(#1389) Bump to Scala 2.12.11
(#1390) Add publishSettings to subprojects.
(#1394) Scalasteward scalatest 3.1.0
(#1397) Mux1H: note results unspecified unless exactly one select signal is high
(#1400) Change BundleLiteral to RecordLiteral
(#1402) expose typeEquivalent
(#1404) Use thread local storage for ChiselContext.
(#1408) Make Counter emit valid FIRRTL
(#1414) Add tests for async reset regs of non-UInt types
(#1417) Revert "Make uselessly public fields in utils private"