v0.24.0

Release notes

• Zero impedance line open at one side NPE (#606)
• AC sensitivity analysis: fix contingency has no impact (#607)
• Update README.md following 0.23.1 release (#609)
• DC sensitivity analysis refactoring (#608)
• Miss contingency status in DC sensitivity analysis (#610)
• Upgrade to PowSyBl parent 9 (#612)
• Connectivity: compute edges/vertices moves from/to main component (#611)
• Fix bug with optional targetDeadBand (#613)
• Connectivity: define main component with given vertex (#617)
• Simplify network parameters creation (#616)
• Refactor everything with new connectivity (#614)
• Clean invalid components logging (#619)
• Fix impedance rescaling (#620)
• Improvements after IOPs (#621)
• Remove useless reset of variant ID, fixing exception when trying to access an uninitialized variant id from a child thread (#623)
• Clean LfGenerator (#626)
• Fix line open at only one side in PropagatedContingency (#627)
• Clean branch limits violation (#628)
• First support of AC security analysis with operator strategies (#590)
• Try to fix AC sensitivity for no impact contingency after normal contingency (#631)
• Use second selector level as fallback selector in NameSlackBusSelector (#632)
• Fix reactive limits outer loop with remote voltage control (70d6c2d)
• Fix network variant removal issue (#637)
• Add new post-contingency status for security analysis and update to 5.0.0-RC1 (#638)
• Fix breaking connectivity elements detection (#639)
• Rework DC security analysis structure and fix StateMonitor (#643)
• Revert starting generator fix (#644)
• Fix loss factor. (#646)
• added test for lines with different nominal voltages at both ends (#648)
• Operator strategy simulation fixes (#633)
• Sensitivity analysis: clean predefined results (#618)
• Simplify variable access from equation term (#649)
• Add range modes MIN_MAX, MAX and TARGET_P to check reactive capability curves (#653)
• Upgrade to PowSyBl Core 5.0.0 (#655)

v0.23.2

Release notes

• Miss contingency status in DC sensitivity analysis (#610)
• Bump powsybl-core to 4.10.1

v0.23.1

Release notes

• AC sensitivity analysis: fix contingency has no impact (#607)
• Zero impedance line open at one side NPE (#606)

v0.23.0

Release notes

• Update PowSyBl Core to 4.10.0 (#604)
• Support of switch contingency in sensitivity analysis and refactoring (#580)
• Check NR state validity (#602)
• Sensitivity analysis: support of dangling line as function reference (active flow and current) (#601)
• Use JGrapht version of core (#600)
• Aggredated loads properties (#592)
• Support multiple add and remove of the same edge in connectivity (#593)
• Fix shunt compensator active power in DC mode (#596)
• Loader post processor selection (#589)
• Remove starting generators from voltage control (#587)
• New GraphConnectivity API (#585)
• Add plausible target voltage parameters. (#586)
• Support of shunt compensator G (#566)

v0.22.1

Release notes

• Add plausible target voltage parameters (#586)

v0.22.0

Release notes

• Workflow trigger updated (#560)
• AC equations optimization (#559)
• Monitor refactoring (#561)
• Limit violations refactoring (#562)
• Support of three windings transformer contingency (#564)
• AC sensitivity analysis: fix contingency has no impact (#563)
• Fix method names for open branch side 2 equations (#567)
• Select slack bus from a voltage level ID (#570)
• Functional logging refactoring (#574)
• Refactor equation vector (#575)
• Largest generator slack bus selector (#577)
• Remove exception of two generators are connected to the same bus but are controlling two different buses. (#578)
• AC security analysis: make contingency propagation optional (#571)
• Security analysis functional logs (#576)
• Fix min impedance check. (19456f0)
• Fix FastMath (#581)
• [Transformer voltage control] Incremental transformer outerloop (#522)
• Zero impedance flows. Specific solution for open Loadflow (#573)

v0.21.0

Release notes

Features

• Use PowSyBl Core 4.9.0 (#540, #557)
  • Replace p0 and q0 of batteries by targetP and targetQ (#547)
  • Distributed active power calculation (#544)
• Update version numbers in readme.md (#521)
• Rename user object to property (#524)
• Remove property (#528)
• Outer loops persistent context (#530)
• Make predefined results for AC and DC sensitivity analyses coherent (#523)
• Use OpenLoadFlow parameter addRatioToLinesWithDifferentNominalVoltageAtBothEnds everywhere (#531)
• Remove transformer voltage controls when no PV buses at non controlled side (#482)
• Injection sensitivity from bus or busbar section ID (#536)
• Contingency refactoring: support of all types of contingencies for AC sensitivity and security analysis (#493)
• Fix LfVscConverterStationImpl design (#546)
• Current limit violations detection in DC security analysis (#549)
• Same provider name for LF, SA and Sensi (#556)

Refactorings and coverage

• Clean phase control outer loop code (#527)
• Equation system index optimization (#435)
• Add AC equations unit tests (a540e79)
• Add unit test for sensi value non regression (#548)
• Improve testing of AC voltage sensitivities (#539)
• Assert active power, reactive power and current consistency (#545)
• AC equations refactoring (#543)
• Optimize cos and sin of ksi (#551)
• Improve transformer voltage control unit testing (#427)
• DC Sensitivity analysis: add unit test on IEEE14 (#555)

Bug fixes

• Fix outer loops cleanup (#514)
• Fixed cases where Q could exceed the generators limits (#529)
• Fix "No such edge in graph" exception (#534)
• Fix AC sensitivity analysis in case of a branch contingency breaking connectivity (#541)
• GraphDecrementalConnectivity fixes:
  • Cache lazily the main connected component in Even-Shiloach implementation (#537)
  • Handle loops in Even-Shiloach implementation (#538)
  • Cut the branch only if connected (8c8064e)

v0.20.0

Release notes

• Use PowSyBl Core 4.8.0 (#480, #509, #518)
• Implements specific parameters from Map (#490)
• AC security analysis cancellation (#491)
• Get original IIDM ID (#494)
• Remove Hvdc Ac emulation OpenLoadFlow parameter (#498)
• Switch contingency support (#501)
• Clean security analysis logs (#519)
• Refactor
  • Clarify buses and branches stored in LfContingency (#504)
  • AC sensitivity analysis: refactoring (#510)
• Various fixes:
  • Fix transformer voltage control with multiple components (#487)
  • Fix: support of non impedant dangling lines (#489)
  • Fix multi components DC LF (#492)
  • Fix security analysis behaviour when network is invalid (#495)
  • Fix HVDC set point increase sensitivity convention (#488)
  • Fix contingency generator for AC computations (#500)
  • Catch MatrixException instead of Exception (#497)
  • DC sensitivity analysis: fix if contingency element is in GLSK (#496)
  • Bug fix: fix network reset (#507)
  • Bug: AC sensitivity analysis with a phase shifter active power control on (#502)
  • Fix DC voltage init (#513)
  • Determinist branchesToOpen order (#516)
  • Fix decremental connectivity (#517)

v0.19.0

Release notes

• Disable switch without removing variables (#455)
• Fix: Hvdc active power setpoint is interpreted on rectifier AC side (#471)
• HVDC AC emulation (#466)
• Remove useless EquationType (#477)
• Remove equation access in Newtow Raphson (#478)
• Bug fix: support of factors with SKIP status after contingencies (#476)

v0.18.0

Release notes

• Fix contingency apply for DC sensitivity calculation and reference flows calculation in case of ZERO status (#468)
• Fix parameters loading (#469)
• Fix KLU issue with regulating phase shifter necessary for connectivity (#460, #467, #470)